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st sitronix ST7625 65k color dot matrix lcd controller/driver ver 1.6 1/160 2008/07 1. introduction the ST7625 is a driver & controller lsi for 65k color graphic dot-matrix liquid crystal display systems. it generates 306 segment and 96 common driver circuits. this chip is connected directly to a microprocessor, accepts seri al peripheral interface (spi) or 8-bit/16-bit parallel display data and stores in an on-chip display data ram. it perf orms display data ram read/write operation with no external operating clo ck to minimize power consumption. in addition, beca use it contains power supply circuits necessary to drive liquid cry stal, it is possible to make a display system with the fewest components. 2. features driver output circuits 306 segment outputs / 96 common outputs applicable duty ratios various partial display partial window moving & data scrolling gray-scale display 4frc & 31 pwm function circuit to display 64 gray-scale display support 8 color mode (idle mode) on-chip display data ram capacity: 102 x 96 x 16 =156,672 bits color support by interface 256 color mode, (rgb)=(332) mode 4k color mode, (rgb)=(444) mode 65k color mode, (rgb)=(565) mode truncated 262k color mode, (rgb)=(666) mode truncated 16m color mode, (rgb)=(888) mode microprocessor interface 8/16-bit parallel bi-directional interface with 68 00-series or 8080-series 4-line serial interface 3-line (9-bits) serial interface on-chip low power analog circuit on-chip oscillator circuit on-chip voltage converter (x2, x3, x4, x5, x6, x7, x8) with internal booster capacitors. extremely few outsider components. (required outsider components: three capacitors) on-chip voltage regulator on-chip electronic contrast control function voltage follower (lcd bias: 1/5~1/12) operating voltage range supply digital voltage (vdd, vdd1): 1.65 to 3.0v supply analog voltage (vdd2, vdd3, vdd4, vdd5): 2.4 to 3.3v lcd driving voltage (vop = v0 - vss): max to 18v lcd driving voltage (otp) contrast adjustment value is stored in the built-in otp-rom for better display quality. lcd driving setting suggestion vop = 11v, bias=1/9. (vdd=2.8v) package type application for cog ST7625-g3 chip thickness=400um ST7625-g4 chip thickness=300um sitronix technology corp. reserves the right to cha nge the contents in this document without prior not ice.
ST7625 ver 1.6 2/160 2008/07 3. ST7625 pad arrangement (cog) chip size : 9,930 um x 820 um bump pitch : pad no. 1 ~ 30, 143 ~ 514 : 27 um (com/seg) pad no. 31 ~ 142 : 80 um (i/o) bump size : pad no. 1 ~ 25, 148 ~ 172 : 120.5 um(x) ~ 15 um(y) (com) pad no. 26 ~ 30, 143 ~ 147, 173 ~ 514 : 15 um(x) ~ 120.5 um(y) (com/seg) pad no. 31 ~ 142 : 65 um(x) ~ 63 um(y) (i/o) bump height : 15 um 32.41 20 41.89 21.89 20 52.41 41.78 30 155.67 125.67 30 11.78 62.77 84.63 30 32.77 54.63 30 unit : um unit : um unit : um 120.5 15 63 15 120.5 65 unit : um bump size of pad 31~142 bump size of pad 1~25 pad 148~172 bump size of pad 26~30 pad 143~147 pad 173~514 (2288,-65) (4693,127) (-4528.36,-351.73)
ST7625 ver 1.6 3/160 2008/07 4. pad center coordinates pad no. pin name x y 001 com[58] -4861.75 320.50 002 com[56] -4861.75 293.50 003 com[54] -4861.75 266.50 004 com[52] -4861.75 239.50 005 com[50] -4861.75 212.50 006 com[48] -4861.75 185.50 007 com[46] -4861.75 158.50 008 com[44] -4861.75 131.50 009 com[42] -4861.75 104.50 010 com[40] -4861.75 77.50 011 com[38] -4861.75 50.50 012 com[36] -4861.75 23.50 013 com[34] -4861.75 -3.50 014 com[32] -4861.75 -30.50 015 com[30] -4861.75 -57.50 016 com[28] -4861.75 -84.50 017 com[26] -4861.75 -111.50 018 com[24] -4861.75 -138.50 019 com[22] -4861.75 -165.50 020 com[20] -4861.75 -192.50 021 com[18] -4861.75 -219.50 022 com[16] -4861.75 -246.50 023 com[14] -4861.75 -273.50 024 com[12] -4861.75 -300.50 025 com[10] -4861.75 -327.50 026 com[8] -4684.02 -306.75 027 com[6] -4657.02 -306.75 028 com[4] -4630.02 -306.75 029 com[2] -4603.02 -306.75 030 com[0] -4576.02 -306.75 031 vpp -4424.71 -329.50 032 vpp -4344.71 -329.50 033 vdd -4264.71 -329.50 pad no. pin name x y 034 cl -4184.71 -329.50 035 cls -4104.71 -329.50 036 vss -4024.71 -329.50 037 vdd -3944.71 -329.50 038 a0 -3864.71 -329.50 039 rw_wr -3784.71 -329.50 040 d0 -3704.71 -329.50 041 d1 -3624.71 -329.50 042 d2 -3544.71 -329.50 043 d3 -3464.71 -329.50 044 d4 -3384.71 -329.50 045 d5 -3304.71 -329.50 046 d6 -3224.71 -329.50 047 d7 -3144.71 -329.50 048 d8 -3064.71 -329.50 049 d9 -2984.71 -329.50 050 d10 -2904.71 -329.50 051 d11 -2824.71 -329.50 052 d12 -2744.71 -329.50 053 d13 -2664.71 -329.50 054 d14 -2584.71 -329.50 055 d15 -2504.71 -329.50 056 vss -2424.71 -329.50 057 vdd -2344.71 -329.50 058 e_rd -2264.71 -329.50 059 /rst -2184.71 -329.50 060 csel -2104.71 -329.50 061 if1 -2024.71 -329.50 062 if2 -1944.71 -329.50 063 if3 -1864.71 -329.50 064 vss -1784.71 -329.50 065 vdd -1704.71 -329.50 066 /cs -1624.71 -329.50
ST7625 ver 1.6 4/160 2008/07 pad no. pin name x y 067 tcap -1544.71 -329.50 068 vdd -1464.71 -329.50 069 vdd -1384.71 -329.50 070 vdd -1304.71 -329.50 071 vdd -1224.71 -329.50 072 vdd1 -1144.71 -329.50 073 vdd1 -1064.71 -329.50 074 vss1 -984.71 -329.50 075 vss1 -904.71 -329.50 076 vss -824.71 -329.50 077 vss -744.71 -329.50 078 vss -664.71 -329.50 079 vss -584.71 -329.50 080 vss2 -504.71 -329.50 081 vss2 -424.71 -329.50 082 vss2 -344.71 -329.50 083 vss2 -264.71 -329.50 084 vss2 -184.71 -329.50 085 vss2 -104.71 -329.50 086 vss2 -24.71 -329.50 087 vss2 55.29 -329.50 088 vss2 135.29 -329.50 089 vss2 215.29 -329.50 090 vss2 295.29 -329.50 091 vss2 375.29 -329.50 092 vss4 455.29 -329.50 093 vss4 535.29 -329.50 094 vdd3 615.29 -329.50 095 vdd3 695.29 -329.50 096 vdd4 775.29 -329.50 097 vdd4 855.29 -329.50 098 vdd5 935.29 -329.50 099 vdd5 1015.29 -329.50 100 vdd5 1095.29 -329.50 101 vdd5 1175.29 -329.50 pad no. pin name x y 102 vdd5 1255.29 -329.50 103 vdd5 1335.29 -329.50 104 vdd5 1415.29 -329.50 105 vdd5 1495.29 -329.50 106 vdd2 1575.29 -329.50 107 vdd2 1655.29 -329.50 108 vdd2 1735.29 -329.50 109 vdd2 1815.29 -329.50 110 vdd2 1895.29 -329.50 111 vdd2 1975.29 -329.50 112 vdd2 2055.29 -329.50 113 vdd2 2135.29 -329.50 114 vdd2 2215.29 -329.50 115 vdd2 2295.29 -329.50 116 vm 2375.29 -329.50 117 vref 2455.29 -329.50 118 v0in 2535.29 -329.50 119 v0in 2615.29 -329.50 120 v0in 2695.29 -329.50 121 v0in 2775.29 -329.50 122 v0s 2855.29 -329.50 123 v0out 2935.29 -329.50 124 v0out 3015.29 -329.50 125 xv0out 3095.29 -329.50 126 xv0out 3175.29 -329.50 127 xv0s 3255.29 -329.50 128 xv0in 3335.29 -329.50 129 xv0in 3415.29 -329.50 130 xv0in 3495.29 -329.50 131 xv0in 3575.29 -329.50 132 vgout 3655.29 -329.50 133 vgout 3735.29 -329.50 134 vgs 3815.29 -329.50 135 vgin 3895.29 -329.50 136 vgin 3975.29 -329.50
ST7625 ver 1.6 5/160 2008/07 pad no. pin name x y 137 vgin 4055.29 -329.50 138 vgin 4135.29 -329.50 139 vgin 4215.29 -329.50 140 vgin 4295.29 -329.50 141 vgin 4375.29 -329.50 142 vgin 4455.29 -329.50 143 com[1] 4576.02 -306.75 144 com[3] 4603.02 -306.75 145 com[5] 4630.02 -306.75 146 com[7] 4657.02 -306.75 147 com[9] 4684.02 -306.75 148 com[11] 4861.75 -327.50 149 com[13] 4861.75 -300.50 150 com[15] 4861.75 -273.50 151 com[17] 4861.75 -246.50 152 com[19] 4861.75 -219.50 153 com[21] 4861.75 -192.50 154 com[23] 4861.75 -165.50 155 com[25] 4861.75 -138.50 156 com[27] 4861.75 -111.50 157 com[29] 4861.75 -84.50 158 com[31] 4861.75 -57.50 159 com[33] 4861.75 -30.50 160 com[35] 4861.75 -3.50 161 com[37] 4861.75 23.50 162 com[39] 4861.75 50.50 163 com[41] 4861.75 77.50 164 com[43] 4861.75 104.50 165 com[45] 4861.75 131.50 166 com[47] 4861.75 158.50 167 com[49] 4861.75 185.50 168 com[51] 4861.75 212.50 169 com[53] 4861.75 239.50 170 com[55] 4861.75 266.50 171 com[57] 4861.75 293.50 pad no. pin name x y 172 com[59] 4861.75 320.50 173 com[61] 4684.02 306.75 174 com[63] 4657.02 306.75 175 com[65] 4630.02 306.75 176 com[67] 4603.02 306.75 177 com[69] 4576.02 306.75 178 com[71] 4549.02 306.75 179 com[73] 4522.02 306.75 180 com[75] 4495.02 306.75 181 com[77] 4468.02 306.75 182 com[79] 4441.02 306.75 183 com[81] 4414.02 306.75 184 com[83] 4387.02 306.75 185 com[85] 4360.02 306.75 186 com[87] 4333.02 306.75 187 com[89] 4306.02 306.75 188 com[91] 4279.02 306.75 189 com[93] 4252.02 306.75 190 com[95] 4225.02 306.75 191 seg[305] 4117.50 306.75 192 seg[304] 4090.50 306.75 193 seg[303] 4063.50 306.75 194 seg[302] 4036.50 306.75 195 seg[301] 4009.50 306.75 196 seg[300] 3982.50 306.75 197 seg[299] 3955.50 306.75 198 seg[298] 3928.50 306.75 199 seg[297] 3901.50 306.75 200 seg[296] 3874.50 306.75 201 seg[295] 3847.50 306.75 202 seg[294] 3820.50 306.75 203 seg[293] 3793.50 306.75 204 seg[292] 3766.50 306.75 205 seg[291] 3739.50 306.75 206 seg[290] 3712.50 306.75
ST7625 ver 1.6 6/160 2008/07 pad no. pin name x y 207 seg[289] 3685.50 306.75 208 seg[288] 3658.50 306.75 209 seg[287] 3631.50 306.75 210 seg[286] 3604.50 306.75 211 seg[285] 3577.50 306.75 212 seg[284] 3550.50 306.75 213 seg[283] 3523.50 306.75 214 seg[282] 3496.50 306.75 215 seg[281] 3469.50 306.75 216 seg[280] 3442.50 306.75 217 seg[279] 3415.50 306.75 218 seg[278] 3388.50 306.75 219 seg[277] 3361.50 306.75 220 seg[276] 3334.50 306.75 221 seg[275] 3307.50 306.75 222 seg[274] 3280.50 306.75 223 seg[273] 3253.50 306.75 224 seg[272] 3226.50 306.75 225 seg[271] 3199.50 306.75 226 seg[270] 3172.50 306.75 227 seg[269] 3145.50 306.75 228 seg[268] 3118.50 306.75 229 seg[267] 3091.50 306.75 230 seg[266] 3064.50 306.75 231 seg[265] 3037.50 306.75 232 seg[264] 3010.50 306.75 233 seg[263] 2983.50 306.75 234 seg[262] 2956.50 306.75 235 seg[261] 2929.50 306.75 236 seg[260] 2902.50 306.75 237 seg[259] 2875.50 306.75 238 seg[258] 2848.50 306.75 239 seg[257] 2821.50 306.75 240 seg[256] 2794.50 306.75 241 seg[255] 2767.50 306.75 pad no. pin name x y 242 seg[254] 2740.50 306.75 243 seg[253] 2713.50 306.75 244 seg[252] 2686.50 306.75 245 seg[251] 2659.50 306.75 246 seg[250] 2632.50 306.75 247 seg[249] 2605.50 306.75 248 seg[248] 2578.50 306.75 249 seg[247] 2551.50 306.75 250 seg[246] 2524.50 306.75 251 seg[245] 2497.50 306.75 252 seg[244] 2470.50 306.75 253 seg[243] 2443.50 306.75 254 seg[242] 2416.50 306.75 255 seg[241] 2389.50 306.75 256 seg[240] 2362.50 306.75 257 seg[239] 2335.50 306.75 258 seg[238] 2308.50 306.75 259 seg[237] 2281.50 306.75 260 seg[236] 2254.50 306.75 261 seg[235] 2227.50 306.75 262 seg[234] 2200.50 306.75 263 seg[233] 2173.50 306.75 264 seg[232] 2146.50 306.75 265 seg[231] 2119.50 306.75 266 seg[230] 2092.50 306.75 267 seg[229] 2065.50 306.75 268 seg[228] 2038.50 306.75 269 seg[227] 2011.50 306.75 270 seg[226] 1984.50 306.75 271 seg[225] 1957.50 306.75 272 seg[224] 1930.50 306.75 273 seg[223] 1903.50 306.75 274 seg[222] 1876.50 306.75 275 seg[221] 1849.50 306.75 276 seg[220] 1822.50 306.75
ST7625 ver 1.6 7/160 2008/07 pad no. pin name x y 277 seg[219] 1795.50 306.75 278 seg[218] 1768.50 306.75 279 seg[217] 1741.50 306.75 280 seg[216] 1714.50 306.75 281 seg[215] 1687.50 306.75 282 seg[214] 1660.50 306.75 283 seg[213] 1633.50 306.75 284 seg[212] 1606.50 306.75 285 seg[211] 1579.50 306.75 286 seg[210] 1552.50 306.75 287 seg[209] 1525.50 306.75 288 seg[208] 1498.50 306.75 289 seg[207] 1471.50 306.75 290 seg[206] 1444.50 306.75 291 seg[205] 1417.50 306.75 292 seg[204] 1390.50 306.75 293 seg[203] 1363.50 306.75 294 seg[202] 1336.50 306.75 295 seg[201] 1309.50 306.75 296 seg[200] 1282.50 306.75 297 seg[199] 1255.50 306.75 298 seg[198] 1228.50 306.75 299 seg[197] 1201.50 306.75 300 seg[196] 1174.50 306.75 301 seg[195] 1147.50 306.75 302 seg[194] 1120.50 306.75 303 seg[193] 1093.50 306.75 304 seg[192] 1066.50 306.75 305 seg[191] 1039.50 306.75 306 seg[190] 1012.50 306.75 307 seg[189] 985.50 306.75 308 seg[188] 958.50 306.75 309 seg[187] 931.50 306.75 310 seg[186] 904.50 306.75 311 seg[185] 877.50 306.75 pad no. pin name x y 312 seg[184] 850.50 306.75 313 seg[183] 823.50 306.75 314 seg[182] 796.50 306.75 315 seg[181] 769.50 306.75 316 seg[180] 742.50 306.75 317 seg[179] 715.50 306.75 318 seg[178] 688.50 306.75 319 seg[177] 661.50 306.75 320 seg[176] 634.50 306.75 321 seg[175] 607.50 306.75 322 seg[174] 580.50 306.75 323 seg[173] 553.50 306.75 324 seg[172] 526.50 306.75 325 seg[171] 499.50 306.75 326 seg[170] 472.50 306.75 327 seg[169] 445.50 306.75 328 seg[168] 418.50 306.75 329 seg[167] 391.50 306.75 330 seg[166] 364.50 306.75 331 seg[165] 337.50 306.75 332 seg[164] 310.50 306.75 333 seg[163] 283.50 306.75 334 seg[162] 256.50 306.75 335 seg[161] 229.50 306.75 336 seg[160] 202.50 306.75 337 seg[159] 175.50 306.75 338 seg[158] 148.50 306.75 339 seg[157] 121.50 306.75 340 seg[156] 94.50 306.75 341 seg[155] 67.50 306.75 342 seg[154] 40.50 306.75 343 seg[153] 13.50 306.75 344 seg[152] -13.50 306.75 345 seg[151] -40.50 306.75 346 seg[150] -67.50 306.75
ST7625 ver 1.6 8/160 2008/07 pad no. pin name x y 347 seg[149] -94.50 306.75 348 seg[148] -121.50 306.75 349 seg[147] -148.50 306.75 350 seg[146] -175.50 306.75 351 seg[145] -202.50 306.75 352 seg[144] -229.50 306.75 353 seg[143] -256.50 306.75 354 seg[142] -283.50 306.75 355 seg[141] -310.50 306.75 356 seg[140] -337.50 306.75 357 seg[139] -364.50 306.75 358 seg[138] -391.50 306.75 359 seg[137] -418.50 306.75 360 seg[136] -445.50 306.75 361 seg[135] -472.50 306.75 362 seg[134] -499.50 306.75 363 seg[133] -526.50 306.75 364 seg[132] -553.50 306.75 365 seg[131] -580.50 306.75 366 seg[130] -607.50 306.75 367 seg[129] -634.50 306.75 368 seg[128] -661.50 306.75 369 seg[127] -688.50 306.75 370 seg[126] -715.50 306.75 371 seg[125] -742.50 306.75 372 seg[124] -769.50 306.75 373 seg[123] -796.50 306.75 374 seg[122] -823.50 306.75 375 seg[121] -850.50 306.75 376 seg[120] -877.50 306.75 377 seg[119] -904.50 306.75 378 seg[118] -931.50 306.75 379 seg[117] -958.50 306.75 380 seg[116] -985.50 306.75 381 seg[115] -1012.50 306.75 pad no. pin name x y 382 seg[114] -1039.50 306.75 383 seg[113] -1066.50 306.75 384 seg[112] -1093.50 306.75 385 seg[111] -1120.50 306.75 386 seg[110] -1147.50 306.75 387 seg[109] -1174.50 306.75 388 seg[108] -1201.50 306.75 389 seg[107] -1228.50 306.75 390 seg[106] -1255.50 306.75 391 seg[105] -1282.50 306.75 392 seg[104] -1309.50 306.75 393 seg[103] -1336.50 306.75 394 seg[102] -1363.50 306.75 395 seg[101] -1390.50 306.75 396 seg[100] -1417.50 306.75 397 seg[99] -1444.50 306.75 398 seg[98] -1471.50 306.75 399 seg[97] -1498.50 306.75 400 seg[96] -1525.50 306.75 401 seg[95] -1552.50 306.75 402 seg[94] -1579.50 306.75 403 seg[93] -1606.50 306.75 404 seg[92] -1633.50 306.75 405 seg[91] -1660.50 306.75 406 seg[90] -1687.50 306.75 407 seg[89] -1714.50 306.75 408 seg[88] -1741.50 306.75 409 seg[87] -1768.50 306.75 410 seg[86] -1795.50 306.75 411 seg[85] -1822.50 306.75 412 seg[84] -1849.50 306.75 413 seg[83] -1876.50 306.75 414 seg[82] -1903.50 306.75 415 seg[81] -1930.50 306.75 416 seg[80] -1957.50 306.75
ST7625 ver 1.6 9/160 2008/07 pad no. pin name x y 417 seg[79] -1984.50 306.75 418 seg[78] -2011.50 306.75 419 seg[77] -2038.50 306.75 420 seg[76] -2065.50 306.75 421 seg[75] -2092.50 306.75 422 seg[74] -2119.50 306.75 423 seg[73] -2146.50 306.75 424 seg[72] -2173.50 306.75 425 seg[71] -2200.50 306.75 426 seg[70] -2227.50 306.75 427 seg[69] -2254.50 306.75 428 seg[68] -2281.50 306.75 429 seg[67] -2308.50 306.75 430 seg[66] -2335.50 306.75 431 seg[65] -2362.50 306.75 432 seg[64] -2389.50 306.75 433 seg[63] -2416.50 306.75 434 seg[62] -2443.50 306.75 435 seg[61] -2470.50 306.75 436 seg[60] -2497.50 306.75 437 seg[59] -2524.50 306.75 438 seg[58] -2551.50 306.75 439 seg[57] -2578.50 306.75 440 seg[56] -2605.50 306.75 441 seg[55] -2632.50 306.75 442 seg[54] -2659.50 306.75 443 seg[53] -2686.50 306.75 444 seg[52] -2713.50 306.75 445 seg[51] -2740.50 306.75 446 seg[50] -2767.50 306.75 447 seg[49] -2794.50 306.75 448 seg[48] -2821.50 306.75 449 seg[47] -2848.50 306.75 450 seg[46] -2875.50 306.75 451 seg[45] -2902.50 306.75 pad no. pin name x y 452 seg[44] -2929.50 306.75 453 seg[43] -2956.50 306.75 454 seg[42] -2983.50 306.75 455 seg[41] -3010.50 306.75 456 seg[40] -3037.50 306.75 457 seg[39] -3064.50 306.75 458 seg[38] -3091.50 306.75 459 seg[37] -3118.50 306.75 460 seg[36] -3145.50 306.75 461 seg[35] -3172.50 306.75 462 seg[34] -3199.50 306.75 463 seg[33] -3226.50 306.75 464 seg[32] -3253.50 306.75 465 seg[31] -3280.50 306.75 466 seg[30] -3307.50 306.75 467 seg[29] -3334.50 306.75 468 seg[28] -3361.50 306.75 469 seg[27] -3388.50 306.75 470 seg[26] -3415.50 306.75 471 seg[25] -3442.50 306.75 472 seg[24] -3469.50 306.75 473 seg[23] -3496.50 306.75 474 seg[22] -3523.50 306.75 475 seg[21] -3550.50 306.75 476 seg[20] -3577.50 306.75 477 seg[19] -3604.50 306.75 478 seg[18] -3631.50 306.75 479 seg[17] -3658.50 306.75 480 seg[16] -3685.50 306.75 481 seg[15] -3712.50 306.75 482 seg[14] -3739.50 306.75 483 seg[13] -3766.50 306.75 484 seg[12] -3793.50 306.75 485 seg[11] -3820.50 306.75 486 seg[10] -3847.50 306.75
ST7625 ver 1.6 10/160 2008/07 pad no. pin name x y 487 seg[9] -3874.50 306.75 488 seg[8] -3901.50 306.75 489 seg[7] -3928.50 306.75 490 seg[6] -3955.50 306.75 491 seg[5] -3982.50 306.75 492 seg[4] -4009.50 306.75 493 seg[3] -4036.50 306.75 494 seg[2] -4063.50 306.75 495 seg[1] -4090.50 306.75 496 seg[0] -4117.50 306.75 497 com[94] -4225.02 306.75 498 com[92] -4252.02 306.75 499 com[90] -4279.02 306.75 500 com[88] -4306.02 306.75 501 com[86] -4333.02 306.75 502 com[84] -4360.02 306.75 503 com[82] -4387.02 306.75 504 com[80] -4414.02 306.75 505 com[78] -4441.02 306.75 506 com[76] -4468.02 306.75 507 com[74] -4495.02 306.75 508 com[72] -4522.02 306.75 509 com[70] -4549.02 306.75 510 com[68] -4576.02 306.75 511 com[66] -4603.02 306.75 512 com[64] -4630.02 306.75 513 com[62] -4657.02 306.75 514 com[60] -4684.02 306.75
ST7625 ver 1.6 11/160 2008/07 5. block diagram
ST7625 ver 1.6 12/160 2008/07 6. pin description 6.1 power supply name i/o description vdd supply power supply for logic circuit (digital vdd 1.65v~3.0v) vdd1 supply power supply for osc circuit (digital vdd 1.65v~3.0v) vdd2 supply power supply for booster circuit (analog vdd 2.4v~3.3v) vdd3 supply power supply for lcd. (analog vdd 2.4v~3.3v) vdd4 supply power supply for lcd. (analog vdd 2.4v~3.3v) vdd5 supply power supply for lcd. (analog vdd 2.4v~3.3v) vss supply ground for logic circuit. ground system sho uld be connected together. vss1 supply ground for osc circuit. ground system should be connected together. vss2 supply ground for booster circuit. ground system sh ould be connected together. vss4 supply ground for lcd. ground system should be conne cted together. 6.2 lcd power supply pins name i/o description v0 out v0 in v0 s i/o positive lcd driver supply voltages. v0 out is the output voltage of v0 generated by ST7625. v0 in is the input pin of power supply to generate v0 vol tage for lcd. v0 s is the input pin of power supply to sense the v0 v oltage. v0 out v0 in & v0 s should be connected together by fpc. xv0 out xv0 in xv0 s i/o negative lcd driver supply voltages. xv0 out is the output voltage of xv0 generated by ST7625. xv0 in is the input pin of power supply to generate xv0 vo ltage for lcd. xv0 s is the input pin of power supply to sense the xv0 v oltage. xv0 out xv0 in & xv0 s should be connected together by fpc. vg out vg in vg s vm i/o bias lcd driver supply voltages. vg out is the output voltage of vg generated by ST7625. vg in is the input pin of power supply to generate vg vol tage for lcd. vg s is the input pin of power supply to sense the vg v oltage. vg out vg in & vg s should be connected together by fpc. vm is the i/o pin of lcd bias supply voltage voltages should have the following relationship; v0 > vg > vm > vss > xv0, 0.7v < vm < vdda-0.7v and 1.8v < vg < 2 x vdda. when the internal power circuit is active, these vo ltages are generated as following table according to the state of lcd bias. note: n = 5 to 12 lcd bias vg vm 1/n bias (2/n) x v0 (1/n) x v0
ST7625 ver 1.6 13/160 2008/07 6.3 system control name i/o description cls i reserved for testing only. please fix this pin to vdd. cl i/o reserved for testing only. leave this pin op en. csel i this pin should connect to vdd. tcap i/o test pin. leave it open. vref o reference voltage output for monitor only. lea ve it open. vpp i when writing otp, it needs external power supply vol tage 7.5v~7.75v (>4 ma) input to write successfully. 6.4 microprocessor interface name i/o description rst i reset input pin, when rst is l, initializatio n is executed. if[3:1] i parallel / serial data input select input if3 if2 if1 mpu interface type h h h 80 series 16-bit parallel l h h 80 series 8-bit parallel l l h 68 series 16-bit parallel h h l 68 series 8-bit parallel h l l 9-bit serial (3 line) l l l 8-bit serial (4 line) note refer to table 7.1.1 for detail serial interface co nnections. /cs i chip select input pins data / instruction i/o is enabled only when /cs is " l". when chip select is non-active, d0 to d15 become high impedance. a0 i register select input pin a0 = "h": d0 to d15 or si are display data a0 = "l": d0 to d15 or si are control command in 3-line or 4-line interface this pin is define to scl. a0 pin is used to input serial clock when the serial interface is selected (scl). (3 line and 4 line)
ST7625 ver 1.6 14/160 2008/07 rw_wr i read / write execution control pin mpu type rw_wr description 6800-series rw read / write control input pin r/w = h : read r/w = l : write 8080-series /wr write enable clock input pin the data on d0 to d15 are latched at the rising edg e of the /wr signal. when in the serial interface, connect it to vdd. e_rd i read / write execution control pin mpu type e_rd description 6800-series e read / write control input pin r/w = h: when e is h, d0 to d15 are in an output status. r/w = l: the data on d0 to d15 are latched at the falling edge of the e signal. 8080-series /rd read enable clock input pin when /rd is l, d0 to d15 are in an output status. when in the serial interface, connect it to vdd. d15 to d0 i/o they connect to the standard 8-bit or 16 bit mpu bus via the 8/16 Cbit bi-directional bus. when the following interface is selected and the /c s pin is high, the following pins become high impedance. 1. in 8-bit parallel: d15-d8 pins are in the state of high impedance should connect to vdd. 2. in 3-line/4-line interface d0 pad will be used f or si function (si) 3. in 4-line interface d1 pad will be used for a0 fu nction 4. in serial interface: unsed pins are in the state of high impedance should connect to vdd. note 1. the mpu interface (control bus and data bus) can not be left floating in any operation mode. 2. unused pins should connect to vdd (supply digital voltage).
ST7625 ver 1.6 15/160 2008/07 6.5 lcd driver outputs name i/o description seg0 to seg305 o lcd segment driver outputs the display data and the frame inversion signal con trol the output voltage of segment driver. segment driver output voltage display data frame inversion (internal) normal display reverse display h h vg vss h l vss vg l h vss vg l l vg vss sleep-in mode vss vss com0 to com95 o lcd common driver outputs the internal scanning data and m signal control the output voltage of common driver. scan data frame inversion (internal) common driver output voltage h h xv0 h l v0 l h vm l l vm sleep-in mode vss
ST7625 ver 1.6 16/160 2008/07 ST7625 i/o pin ito resister limitation pin name ito resister vdd, vdd1~vdd5, vss,vss1,vss2,vss4 <100 v0 in , v0 out , v0 s ,xv0 in , xv0 out ,xv0 s , vg in , vg out ,vg s ,vm <300 vpp <50 a0, e_rd, rw_wr, /cs, d0 d15, (si), (scl) <1k /rst <10k if[3:1], cls, csel <1k tcap, cl, vref floating note: 1. make sure that the ito resistance of com0 ~ com6 9 is equal, and so is it of seg0 ~ seg293. these limitations include the bottleneck of ito lay out. 2. to avoid the noise in different power system aff ect other power system, please separate different p ower source on ito layout. 3. the v0, xv0 and vg power circuits have output pins, input pins and a sensor input. to avoid the power noise affects the sensor of the power circuits. the trace should be s eparated by ito and should be connected together by fpc. vdd vdd2 vdd3 driverside vddx fpc pin fpc pin shortbyfpc separated by ito separated by ito driverside fpc pin fpc pin shortbyfpc
ST7625 ver 1.6 17/160 2008/07 7. functional description 7.1 microprocessor interface chip select input /cs pin is chip selection. the ST7625 is active when /cs=l. in serial interface mode, the internal shift register and the counter are reset when /cs=h. 7.1.1 selecting parallel / serial interface ST7625 has six types of interface with an mpu, which are two serial and four parallel interfaces. the pa rallel or serial interface is determined by if pin as shown in table 7.1.1 . table 7.1.1 parallel / serial interface mode i/f mode pin assignment if1 if2 if3 i/f description /cs a0 e_rd rw_wr d15 to d8 d7 to d2 d0 d1 h h h 80 serial 16-bit parallel /cs a0 /rd /wr d15 ~ d8 d7 ~ d2 d0 d1 h h l 80 serial 8-bit parallel /cs a0 /rd /wr -- d7 ~ d2 d0 d1 h l l 68 serial 16-bit parallel /cs a0 e r/w d15 ~ d8 d7 ~ d2 d0 d1 l h h 68 serial 8-bit parallel /cs a0 e r/w -- d7 ~ d2 d0 d1 l l l 8-bit spi mode (4 line) /cs scl -- -- -- -- si a0 l l h 9-bit spi mode (3 line) /cs scl -- -- -- -- si -- note: when these pins are set to any other combinati on, a0, e_rd and rw_wr inputs are disabled and d0 to d15 are high impedance. 7.1.2 8-bit or 16-bit parallel interface the ST7625 identifies the type of the data bus signa ls according to the combination of a0, /rd (e) and /w r (w/r) signals, as shown in table 7.1.2. table 7.1.2 parallel data transfer common 6800-series 8080-series a0 r/w e /wr /rd description h h h display data read out h h h register status read l l h insturction write h l h display data write
ST7625 ver 1.6 18/160 2008/07 /wr /rd displaydata readout displaydata write instruction write registerstatus read 8080series a0 figure 7.1parallel data transfer example chart relation between data bus and gradation data the interface of ST7625 supports 256 color display,4 096 color display, 65k color display, truncated 262k color display, and truncated 16m color display. when using 256, 4096, 65k, 262k, and 16m color displa y; you can specify color for each of r, g, b using t he palette function. use the command for switching between these modes. (1) 256 color input mode 1. 8-bit interface d7, d6, d5, d4, d3, d2, d1, d0: rrr ggg bb 1st writes there is only 1 write operation for 1 pixel data. the data of a single pixel is written in the displa y data ram when the 1 st write operation finishes.
ST7625 ver 1.6 19/160 2008/07 (2) 4096-color display (1-1) type a 4096 color display 1. 8-bit interface d7, d6, d5, d4, d3, d2, d1, d0: rrrr gggg 1st writes d7, d6, d5, d4, d3, d2, d1, d0: bbbb rrrr 2nd writes d7, d6, d5, d4, d3, d2, d1, d0: gggg bbbb 3rd writes there are 3 write operations for 2 pixel data. the data of a single pixel is written in the displa y data ram when the 2 nd write operation finishes, and the 2 nd pixel data is written in the display data ram when the 3 rd write operation finishes. (1-2) type b 4096 color display 1. 8-bit interface d7, d6, d5, d4, d3, d2, d1, d0: xxxx rrrr 1st writes d7, d6, d5, d4, d3, d2, d1, d0: gggg bbbb 2nd writes there are 2 write operations for 1 pixel data. the data of a single pixel is written in the displa y data ram when the the 2 nd write operation finishes. x are ignored dummy bits. 2. 16-bit interface d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d 4, d3, d2, d1, d0: xxxx rrrr gggg bbbb there is only 1 write operation for 1 pixel data. the data of a single pixel is written in the displa y data ram when the 1 st write operation finishes. x are ignored dummy bits. (3) 65k color input mode 1. 8-bit interface d7, d6, d5, d4, d3, d2, d1, d0: rrrrr ggg 1st writes d7, d6, d5, d4, d3, d2, d1, d0: ggg bbbbb 2nd writes there are 2 write operations for 1 pixel data. the data of a single pixel is written in the displa y data ram when the 2 nd write operation finishes. 2. 16-bit interface d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d 4, d3, d2, d1, d0: rrrrr gggggg bbbbb 1st writes there is only 1 write operation for 1 pixel data. the data of a single pixel is written in the displa y data ram when the 1 st write operation finishes.
ST7625 ver 1.6 20/160 2008/07 (4) truncated 262k color input mode 1. 8-bit interface d7, d6, d5, d4, d3, d2, d1, d0: rrrrrr xx 1st writes d7, d6, d5, d4, d3, d2, d1, d0: gggggg xx 2nd writes d7, d6, d5, d4, d3, d2, d1, d0: bbbbbb xx 3rd writes the data of a single pixel is read after the third write operation as shown, and it is written in the display ram. x is dummy bit, and it is ignored for display. 2. 16-bit interface d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d 4, d3, d2, d1, d0: rrrrrr xx gggggg xx 1st writes d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d 4, d3, d2, d1, d0: bbbbbb xxxxxxxxxxxx 2nd writes the data of a single pixel is read after the second write operation as shown, and it is written in the display ram. (5) truncated 16m color input mode 1. 8-bit interface d7, d6, d5, d4, d3, d2, d1, d0: rrrrrrrr 1st writes d7, d6, d5, d4, d3, d2, d1, d0: gggggggg 2nd writes d7, d6, d5, d4, d3, d2, d1, d0: bbbbbbbb 3rd writes the data of a single pixel is read after the third write operation as shown, and it is written in the display ram. 2. 16-bit interface d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d 4, d3, d2, d1, d0: rrrrrrrr gggggggg 1st writes d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d 4, d3, d2, d1, d0: bbbbbbbb xxxxxxxx 2nd writes the data of a single pixel is read after the second write operation as shown, and it is written in the display ram.
ST7625 ver 1.6 21/160 2008/07 7.1.3 8-bit and 9-bit serial interface the 8-bit serial interface uses four pins /cs, si, scl , and a0 to enter commands and data. meanwhile, the 9-bit serial interface uses three pins /cs, si and scl for the same purpose. data read is not available in the serial interface. data entered must be 8 bits for each time. the relation between gray-scale data and data bus i n the serial input is the same as that in the 8-bit parallel interface mode at every gradation. (1) 8-bit serial interface (4-line) when entering data (parameters): a0= high at the ris ing edge of the 8 th scl. when entering command: a0= low at the rising edge o f the 8 th scl when entering reading command:
ST7625 ver 1.6 22/160 2008/07 (2) 9-bit serial interface (3-line) when entering data (parameters): si= high at the ris ing edge of the 1 st scl. when entering command: si= low at the rising edge of the 1 st scl. when entering reading command: if /cs is set to high while the 8 bits from d7 to d 0 are entered, the data concerned is invalidate. bef ore entering succeeding sets of data, you must correctly input t he data concerned again. in order to avoid data transfer error due to incom ing noise, it is recommended to set /cs at high on b yte basis to initialize the serial-to-parallel conversion counte r and the register when executing the command ramwr, set /cs to high a fter writing the last address. the internal shift r egister and the counter will reset when /cs =h.
ST7625 ver 1.6 23/160 2008/07 7.1.4 8-bit and 9-bit serial interface data color c oding 8-bit serial interface (4-line) (1) r 3-bit, g 3-bit, b 2-bit, 256 colors (2) r 4-bit, g 4-bit, b 4-bit, 4,096 colors C type a r2 r1 r0 g3 g2 g1 g0 r3 b3 b2 b1 b9 r3 r2 r1 r0 g3 g2 g2 g0 b3 b2 b1 b0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 /cs si scl pixel n pixel n+1 12 bit to 16 bit g1 r1 b3 g3 r3 b2 g2 r2 b1 frame memory note: r3, g3, b3 are the most significant bits and r0, g0, b0 are the least significant bits. there are 2 pixel ( = 3 sub-pixels ) per 3 byte. a0
ST7625 ver 1.6 24/160 2008/07 (3) r 4-bit, g 4-bit, b 4-bit, 4,096 colors C type b (4) r 5-bit, g 6-bit, b 5-bit, 65,536 colors
ST7625 ver 1.6 25/160 2008/07 (5) r 6-bit, g 6-bit, b 6-bit, 262k colors (6) r 8-bit, g 8-bit, b 8-bit, 16m colors
ST7625 ver 1.6 26/160 2008/07 9-bit serial interface (3-line) (1) r 3-bit, g 3-bit, b 2-bit, 256 colors (2) r 4-bit, g 4-bit, b 4-bit, 4,096 colors C type a
ST7625 ver 1.6 27/160 2008/07 (3) r 4-bit, g 4-bit, b 4-bit, 4,096 colors C type b (4) r 5-bit, g 6-bit, b 5-bit, 65,536 colors
ST7625 ver 1.6 28/160 2008/07 (5) r 6-bit, g 6-bit, b 6-bit, 262k colors r6 r5 r4 r3 r2 x x r7 1 g7 g6 g5 g4 g3 g2 x x 1 b7 b6 b5 b4 b3 1 b2 x x d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 /cs si scl pixeln g1 r1 b3 g3 r3 b2 g2 r2 b1 frame memory note:r7,g7,b7arethemostsignificantbitsandr2, g2,b2aretheleast significantbits. thereis1pixel(=3subpixels)per3byte. 18bitto16bit (6) r 8-bit, g 8-bit, b 8-bit, 16m colors r6 r5 r4 r3 r2 r1 r0 r7 1 g7 g6 g5 g4 g3 g2 g1 g0 1 b7 b6 b5 b4 b3 1 b2 b1 b0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 /cs si scl pixeln g1 r1 b3 g3 r3 b2 g2 r2 b1 frame memory note:r7,g7,b7arethemostsignificantbitsandr0, g0,b0aretheleast significantbits. thereis1pixel(=3subpixels)per3byte. 24bitto16bit
ST7625 ver 1.6 29/160 2008/07 7.2 access to ddram and internal registers ST7625 realizes high-speed data transfer because the access from mpu is a sort of pipeline processing do ne via the bus holder attached to the internal, requiring the cycl e time alone without needing the wait time. for example, when mpu writes data to the ddram, the d ata is once held by the bus holder and then written to the ddram before the succeeding write cycle is started. when mpu reads data from the ddram, the first read cycle is dummy and the bus holder holds the data read in the dummy cycle, and then it read from the bus holder to the system bus in the succeeding read cycle. figure 7.2 illustrates these relations. in 80-series interface mode: n dummy d (n ) d (n +1) mpusignal a0 data internalsignals addresscounter /rd n d (n ) d (n +1) d (n +2) d (n +3) internallatch read operation /wr /wr /rd d (n ) d (n +1) d (n +2) figure 7.2
ST7625 ver 1.6 30/160 2008/07 7.3 display data ram (ddram) 7.3.1 ddram it is 102 x 96 x 16 bits capacity ram prepared for s toring dot data. refer to the following memory map for the ram configuration. memory map rgb alignment data control command column 0 1 101 (madctr) mx=0 101 100 0 (madctr) mx=1 color r g b r g b r g b data page (madctr) my=0 (madctr) my=1 0 95 1 94 2 93 3 92 4 91 5 90 6 89 7 88 : : 88 7 89 6 90 5 91 4 92 3 93 2 94 1 95 0 segout 0 1 2 3 4 5 303 304 305 you can change position of r and b with madctr comma nd.
ST7625 ver 1.6 31/160 2008/07 7.3.2 address counter the address counter sets the addresses of the displ ay data ram for writing. data is written pixel into the ram matrix of ST7625. the data for one pixel or two pixels is collected (rgb 5-6-5-bit), according to the data formats. as soon as this pixel -data information is complete, the write access i s activated on the ram. the locations of ram are addressed by the addre ss pointers. the address ranges are x=0 to x=101 (6 5hex) and y=0 to y=95 (5fh). addresses outside these ranges a re not allowed. before writing to the ram, a window must be defined i nto which will be written. the window is programmab le via the command registers xs, ys designating the start addres s and xe, ye designating the end address. for example the whole display contents will be writ ten, the window is defined by the following values: xs=0 (0h) ys=0 (0h) and xe=101 (65h), ye=95 (5fh). in vertical addressing mode (mv=1), the y-address in crements after each byte, after the last y-address (y=ye), y wraps around to ys and x increments to address the next co lumn. in horizontal addressing mode (mv=0), the x-ad dress increments after each byte, after the last x-addres s (x=xe), x wraps around to xs and y increments to ad dress the next row. after the every last address (x=xe and y=ye) the address pointers wrap around to address (x=xs and y= ys). for flexibility in handling a wide variety of display a rchitectures, the commands caset, raset and madctr (se e section 9.1.21), define flags mx and my, which allows mir roring of the x-address and y-address. all combinati ons of flags are allowed. figure 7.3 show the available combinations of writing to the display ram. when mx, my and mv wi ll be changed the data must be rewritten to the display ram. for each image condition, the controls for the colu mn and row counters apply as below: condition column counter row counter when ramwr command is accepted return to start column (xs) return to start row (ys) complete pixel read / write action increment by 1 no change the column counter value is larger than end column (xe) return to start column (xs) increment by 1 the column counter value is larger than end column (xe) and the row counter value is larger than end row (ye) return to start column (xs) return to start row (ys)
ST7625 ver 1.6 32/160 2008/07 madctr parameter display data direction mv mx my image in the host (mpu) image in the driver (ddram) normal 0 0 0 y-mirror 0 0 1 x-mirror 0 1 0 x-mirror y-mirror 0 1 1 x-y exchange 1 0 0 x-y exchange y-mirror 1 0 1 x-y exchange x-mirror 1 1 0 x-y exchange x-mirror y-mirror 1 1 1 figure 7.3 frame data write direction according to the madctr para meters (mv, mx and my)
ST7625 ver 1.6 33/160 2008/07 7.3.3 i/o buffer circuit it is the bi-directional buffer used when mpu reads or writes the ddram. since mpus read or write of ddram is performed independently from data output to the dis play data latch circuit, asynchronous access to the ddram when the lcd is turned on does not cause troubles such as fl icking of the display images. 7.3.4 scroll address circuit the circuit associates lines on ddram with com outp ut. ST7625 processes signals for the liquid crystal display on 1-line basis. thus, when specifying a specific area in the area scroll display or partial display, you must d esignate it in line. 7.3.5 display data latch circuit this circuit is used to temporarily hold display da ta to be output from the ddram to the seg decoder circ uit. since display normal/inverse and display on/off commands are used to control data in the latch circuit alone, they d o not modify data in the ddram.
ST7625 ver 1.6 34/160 2008/07 7.3.6 normal display on or partial mode on, vertica l scroll off in this mode, contents of the frame memory within a n area where column address is 00h to 65h and row a ddress is 00h to 5fh is displayed. to display a dot on leftmost top corner, store the dot data at (column address, row address) = (0,0). example1) normal display on example2) partial display on: psl[6:0] = 04h, pel[6:0] = 5eh, madctr (ml)=0
ST7625 ver 1.6 35/160 2008/07 7.3.7 vertical scroll rolling scroll there is just one type of vertical scrolling, which is determined by the commands vertical scrolling d efinition (33h) and vertical scrolling start address (37h). figure 7.4 rolling scroll definition when vertical scrolling definition parameters (tfa+vsa+bfa) =96. in this case, rolling scrolling is applied as shown below. all the memory contents will be used. example1) panel size=102 x 96, tfa =3, vsa=91, bfa=2, ssa=4, madctr (ml) =0: rolling scroll seg0 :: : seg98 seg4 seg3 seg2 seg1 seg99 seg10 0 seg10 1
ST7625 ver 1.6 36/160 2008/07 example2) panel size=102 x 96, tfa =3, vsa=91, bfa=2, ssa=4, madctr (ml) =1: rolling scroll seg0 :: : seg98 seg4 seg3 seg2 seg1 seg99 seg10 0 seg10 1
ST7625 ver 1.6 37/160 2008/07 vertical scroll example there are 2 types of vertical scrolling, which are determined by the commands vertical scrolling def inition (33h) and vertical scrolling start address (37h). case 1: tfa + vsa + bfa<96 n/a. do not set tfa + vsa + bfa<96. in that case, unexpect ed picture will be shown. case 2: tfa + vsa + bfa=96 (rolling scrolling) example1) when madctr parameter ml=0, tfa=0, vsa=96, bf a=0 and vscsad=40. 1 2 1 1 2 1 2 2
ST7625 ver 1.6 38/160 2008/07 example2) when madctr parameter ml=1, tfa=10, vsa=86, bfa=0 and vscsad=30. 1 1 2 1 2 3 3 1 3 2 3 2
ST7625 ver 1.6 39/160 2008/07 7.4 gray-scale display ST7625 incorporates a 4frc & 31 pwm function circuit to display a 64 gray-scale display. 7.5 oscillation circuit ST7625 has a built-in an oscillator circuit. it prov ides internal clock without using external resistor . this oscillator signal is used in the voltage converter and display timing ge neration circuit. 7.6 display timing generator circuit this circuit generates some signals for displaying lcd. the display clock, which is generated by oscil lation clock, generates the clock for the line counter and the si gnal for the display data latch. the line address o f on-chip ram is generated in synchronization with the display clock and the display data latch circuit latches the 96- bits display data in synchronization with the display clock. the display data, which is read to the lcd driver, is complete ly independent of the access to the display data ram from the microproces sor. the display clock generates an lcd ac signal (m ), which enables the lcd driver to make an ac drive waveform, and also generates an internal common timing signa l and start signal to the common driver. the frame signal or th e line signal changes the m by setting internal ins truction. driving waveform and internal timing signal are shown in fi gure 7.5. figure 7.5 2-frame ac driving waveform (duty ratio: 1/96)
ST7625 ver 1.6 40/160 2008/07 figure 7.6 n-line inversion driving waveform (n=10, duty ratio=1/96)
ST7625 ver 1.6 41/160 2008/07 7.7 power level definition 7.7.1 power on/off sequence definitation: vddi=vdd & vdd1; vdda=vdd2, vdd3, vdd4 & vdd 5 during power off, if lcd is in the sleep out mode, vd da and vddi must be powered down minimum 120m sec aft er /rst has been released. during power off, if lcd is in the sleep in mode, vdd i or vdda can be powered down minimum 0msec after /rst has been released. /cs can be applied at any timing or can be permanent ly grounded. /rst has priority over /cs. if /rst line is not held stable by host during power on sequence as defined in sections case1 and case2, t hen it will be necessary to apply a hardware reset (/rst) after hos t power on sequence is complete to ensure correct ope ration. otherwise function is not guaranteed. the power on/off sequence is illustrated below: /rst line is held high or unstable by host at powe r on if /rst line is held high or unstable by the host du ring power on, then a hardware reset must be applied after both vdda and vddi have been applied C otherwise correct funct ionality is not guaranteed. there is no timing rest riction upon this hardware reset. note: unless otherwise specified, timings herein sh ow cross point at 50% of signal/power level.
ST7625 ver 1.6 42/160 2008/07 7.7.2 power levels 6 level modes are defined they are in order of maxi mum power consumption to minimum power consumption: 1. normal mode on (full display), idle mode off, sl eep out: in this mode, the display is able to show maximum 6 5k colors. 2. partial mode on, idle mode off, sleep out: in this mode part of the display is used with maxim um 65k colors. 3. normal mode on (full display), idle mode on, sle ep out: in this mode, the full display area is used but wit h 8 colors. 4. partial mode on, idle mode on, sleep out: in this mode, part of the display is used but with 8 colors. 5. sleep in mode: in this mode, the dc:dc converter, internal oscilla tor and panel driver circuit are stopped. only the mcu interface and memory works with digital vdd power supply. contents of the memory are safe. 6. power off mode: in this mode, both analog vdd and digital vdd are remo ved. note: transition between modes 1-5 is controllable by mcu commands. mode 6 is entered only when both po wer supplies are removed.
ST7625 ver 1.6 43/160 2008/07 7.8 liquid crystal driver power circuit the power supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. there are vo ltage converter circuits, voltage regulator circuit s, and voltage follower circuits. they are controlled by power con trol instruction. dc/dc booster block diagram
ST7625 ver 1.6 44/160 2008/07 7.8.1 voltage regulator circuits there is a built-in voltage regulator circuits in st 7625 for generating v0. after internal voltage is re gulated by voltage regulator circuit, v0 is generated. detail explanati on of v0 set is listed below: 7.8.1.1 set v0 (temperature = 24 ) v0=a+{vop[8:0] + vopoffset[8:0]+ (ev[6:0]-3fh)}xb (v) example: vop[8:0]=011010010 vopoffset[8:0]=000000011 ev[6:0]=0111111 v0=3.6 + { 210 + 3 + (63-63) } x 0.04 =12.12 (v) a is a fixed constant value (seetable 7.8.1). b is a fixed constant value (seetable 7.8.1). vop [8:0] is the programmed vop value. the programmi ng range for vop[8:0] is 5 to 410 (019ahex). the range of contrast is 128 steps for fine tuning vop. table 7.8.1 symbol value unit a 3.6 v b 0.04 v the vop [8:0] value must be in the v0 programming ran ge as given in figure 7.7. evaluating v0 equation, va lues outside the programming range indicated in many res ult.v0 range is 3.6 ~18. figure 7.7 v0 programming range
ST7625 ver 1.6 45/160 2008/07 as the programming range for the internally generate d v0 voltage is above the limited v0 (18v), users hav e to ensure while setting the vpr register and selecting the temperatu re compensation that under all conditions and inclu ding all tolerances that the v0 voltage remains below 18v. 7.8.1.2 set v0 with temperature compensation (tempe ratue 24 ) there are 16-line slope in each temperature steps a nd customer can select one line slope of temperatur e compensation coefficient for each temperature step. each temperature step is 8 o c. please see figure 7.8 as below. 40 32 ~ 8 16 24 32 40 80 88 16lineslope v0(v) ~ temperature ( o c) figure 7.8
ST7625 ver 1.6 46/160 2008/07 in command tempsel each mtx, where x=0, 1, 2,, e, f, h as a value between 0 and 15. mtx = 0 results in 0v increment on v0, mtx = 1 results in mx=5mv increment, , mtx = 15 results in mx=15x5mv=75mv increment. not e that each mtx individually corresponds to a temperature interval; the relations between mx and v0 quantity d ue to temperature v0(t) are described in the equations shown as follow s: temperature range equation v0(v) at temperature= t -40 t -32 v0(t) = v0(t 24 )+ (-32-t) m0 +( m1 + m2 + m3 + m4 + m5 + m6 + m7) 8 -32 t -24 v0(t) = v0(t 24 )+ (-24-t) m1 +( m2 + m3 + m4 + m5 + m6 + m7) 8 -24 t -16 v0(t) = v0(t 24 )+ (-16-t) m2 +( m3 + m4 + m5 + m6 + m7) 8 -16 t -8 v0(t) = v0(t 24 )+ (-8-t) m3 +( m4 + m5 + m6 + m7) 8 -8 t 0 v0(t) = v0(t 24 )+ (0-t) m4 +( m5 + m6 + m7) 8 0 t 8 v0(t) = v0(t 24 )+ (8-t) m5 +( m6 + m7) 8 8 t 16 v0(t) = v0(t 24 )+ (16-t) m6 + m7 8 16 t 24 v0(t) = v0(t 24 )+ (24-t) m7 24 t 32 v0(t) = v0(t 24 ) (t-24) m8 32 t 40 v0(t) = v0(t 24 ) (t-32) m9 m8 8 40 t 48 v0(t) = v0(t 24 ) (t-40) m10 (m9 + m8 ) 8 48 t 56 v0(t) = v0(t 24 ) (t-48) m11 (m10 + m9 + m8 ) 8 56 t 64 v0(t) = v0(t 24 ) (t-56) m12 (m11 + m10 + m9 + m8 ) 8 64 t 72 v0(t) = v0(t 24 ) (t-64) m13 (m12 + m11 + m10 + m9 + m8 ) 8 72 t 80 v0(t) = v0(t 24 ) (t-72) m14 (m13 + m12 + m11 + m10 + m9 + m8 ) 8 80 t 88 v0(t) = v0(t 24 ) (t-80) m15 ( m14 + m13 + m12 + m11 + m10 + m9 + m8 ) 8 note: please make sure to avoid any kind of heating sourc e closing to ST7625 such as back light, to prevent the vop value is not as anticipated because of temp erature compensate circuit functioning.
ST7625 ver 1.6 47/160 2008/07 setting example for default tc curve command 0xf4 data 1 st : 0xff 2 nd : 0x36 3 rd : 0x04 4 th : 0x00 5 th : 0x33 6 th : 0x42 7 th : 0xc4 8 th : 0x59 bias=1/9, vop= 11v, default tc 0 2 4 6 8 10 12 14 16 18 -30 -20 -10 0 10 20 30 40 50 60 70 80 temp. vop default tc
ST7625 ver 1.6 48/160 2008/07 setting example for tc curve=-0.04% command 0xf4 data 1 st : 0x11 2 nd : 0x11 3 rd : 0x11 4 th : 0x11 5 th : 0x11 6 th : 0x11 7 th : 0x11 8 th : 0x11 vop=11v, bias=1/9,tc=-0.04% 0 2 4 6 8 10 12 14 16 18 -40 -30 -20 -10 0 10 20 24 30 40 50 60 70 80 90 temp vop tc=-0.04%
ST7625 ver 1.6 49/160 2008/07 setting example for tc curve=-0.08% command 0xf4 data 1 st : 0x22 2 nd : 0x22 3 rd : 0x22 4 th : 0x22 5 th : 0x22 6 th : 0x22 7 th : 0x22 8 th : 0x22 vop=11v, bias=1/9,tc=-0.08% 0 2 4 6 8 10 12 14 16 18 -40 -30 -20 -10 0 10 20 24 30 40 50 60 70 80 90 temp vop tc=-0.08%
ST7625 ver 1.6 50/160 2008/07 setting example for tc curve = -0.12% command 0xf4 data 1 st : 0x33 2 nd : 0x33 3 rd : 0x33 4 th : 0x33 5 th : 0x33 6 th : 0x33 7 th : 0x33 8 th : 0x33 vop=11v, bias=1/9,tc=-0.12% 0 2 4 6 8 10 12 14 16 18 -40 -30 -20 -10 0 10 20 24 30 40 50 60 70 80 90 temp vop tc=-0.12%
ST7625 ver 1.6 51/160 2008/07 7.8.1.3 v0 fine tuning ST7625 has 2 commands for fine tuning v0. these comma nds are vopofsetinc and vopofsetdec. when writing vopofsetinc into ic for each time, v0 would increase 40mv; when writing vopofsetdec into ic for each time , v0 would decrease 40mv. example: vop[8:0]=011010010 vopoffset[8:0]=000000011 ev[6:0]=0111111 vopofsetinc x2 v0=3.6 + { 210 +3+ (63-63) } x 0.04 + 0.04x2 =12.2 (v) 7.8.2 voltage follower circuits there is a built-in voltage follower circuits in st7 625 for generating vg and vm. these voltages are dec ided by bias ratio selection circuitry which is set by users with soft ware code. the selection of 1/5 to 1/12 bias ratios can match the optimum display performance of lcd panel. bias driving rule is listed below: lcd bias vg vm 1/n bias (2/n) x v0 (1/n) x v0 n=5 to 12 7.8.3 otp setting flow otp setting flow ST7625 provide the write and read function to write the electronic control value and built-in resistance ratio into and read them from the built-in otp. using the write and rea d functions, you can store these values appropriate to each lcd panel. this function is very convenient for user in settin g from some different panels voltage. but using thi s function must attention the setting procedure. please see the foll owing diagram. figure 7.9 v0 value control for different modules by loading o tp offset note1: this setting flow is used for lcm assembler. note2: otp shouldnt be written without preceding l oading correctly from otp to avoid some errors duri ng ic operation. note3: when writing value to otp, the voltage of vp p must be within 7.5v~7.75v; the current of ivpp mu st be more than 4 ma. note4: if the otp is exposed to a high temperature for hours, data in the memory cell may probably be lost before the data retention guarantee period. to retain data in the memory cell , keep the memory cell below 90 . the data retention guarantee period is specified including the retention period.
ST7625 ver 1.6 52/160 2008/07 7.8.4 frquency temperature gradient compensation co efficient ST7625 will auto-switch frame rate on different temp erature shown in figure 7.10. ta, tb and tc are frame rate switching temperatures which can be defined by cust omer with command tmprng. fa, fb, fc and fd are switch ed frame rate which also can be defined by customer wi th command frmsel. the frame rate range is from 37.5hz to 170hz. when the temperature is in increasing state, frame rate changes to the higher step at ta/tb/tc+th( ). whe n the temperature is in decreasing state, frame rate chan ges to the lower step at ta/tb/tc. for example: tc=10 and th=5 , fc switches to fd at 15 but fd switches to fc at 10 . please take figure 7.10for reference. figure 7.10
ST7625 ver 1.6 53/160 2008/07 8. reset value item after power on after software reset after hardware reset frame memory (ram data) random no change no change sleep in/out in in in display mode (normal/partial) normal normal normal display inversion on/off off off off all pixel off mode disable disable disable all pixel on mode disable disable disable contrast (ev) 3fh 3fh 3fh display on/off display off display off display off column: start address (xs) 00h 00h 00h column: end address (xe) 65h 65h 65h row: start address (ys) 00h 00h 00h row: end address (ye) 5fh 5fh 5fh partial: start address (ps) 00h 00h 00h partial: end address (pe) 5fh 5fh 5fh scroll: top fixed area (tfa) 00h 00h 00h scroll: scroll area (vsa) 65h 65h 65h scroll: bottom fixed area (bfa) 00h 00h 00h memory data access control my/mx/mv/ml/rgb) 0/0/0/0/0 no change 0/0/0/0/0 scroll start address (ssa) 00h 00h 00h idle mode on/off off off off interface color pixel format (p) 05h (16bit/pixel) no change 05h (16bit/pixel) drive duty 5fh 5fh 5fh first common 00h 00h 00h fosc divider no division no division no division common scan direction 0 47, 48 95 0 47, 48 95 0 47, 48 95 vop 0d2h 0d2h 0d2h bias 1/9 bias 1/9 bias 1/9 bias booster setting 8x 8x 8x booster efficiency 01 01 01 vg source from 2vdd2 from 2vdd2 from 2vdd2 epctin 0 0 0 otp selection disable disable disable frame frequency in normal color (fa/fb/fc/fd) 46hz/61.5hz/72/hz/77hz 46hz/61.5hz/72/hz/77hz 46hz/61.5hz/72/hz/77hz temperature range (ta/tb/tc) -10 /0 /10 -10 /0 /10 -10 /0 /10 temperature hysteresis (th for frame rate) 5 5 5
ST7625 ver 1.6 54/160 2008/07 9. instructions 9.1 instruction table command table-1 hex command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 function ref (00h) nop 0 1 0 0 0 0 0 0 0 0 0 no operation 9.1.1 (01h) swreset 0 1 0 0 0 0 0 0 0 0 1 software reset 9.1.2 (09h) rddst 0 1 0 0 0 0 0 1 0 0 1 read display status 9.1.3 - 1 0 1 - - - - - - - - dummy read - 1 0 1 st31 st30 st29 st28 st27 st26 st25 st24 (d31-d24) - 1 0 1 st23 st22 st21 st20 st19 st18 st17 st16 (d23-d16) - 1 0 1 st15 st14 st13 st12 st11 st10 st9 st8 (d15-d8) - 1 0 1 st7 st6 st5 st4 st3 st2 st1 st0 (d7-d0) (10h) slpin 0 1 0 0 0 0 1 0 0 0 0 sleep in & booster off 9.1.4 (11h) slpout 0 1 0 0 0 0 1 0 0 0 1 sleep out & booster on 9.1.5 (12h) ptlon 0 1 0 0 0 0 1 0 0 1 0 partial mode on 9.1.6 (13h) noron 0 1 0 0 0 0 1 0 0 1 1 partial off (normal) 9.1.7 (20h) invoff 0 1 0 0 0 1 0 0 0 0 0 display inversion off (normal) 9.1.8 (21h) invon 0 1 0 0 0 1 0 0 0 0 1 display inversion on 9.1.9 (22h) apoff 0 1 0 0 0 1 0 0 0 1 0 all pixel off (only for test purpose) 9.1.10 (23h) apon 0 1 0 0 0 1 0 0 0 1 1 all pixel on (only for test purpose) 9.1.11 (25h) wrcntr 0 1 0 0 0 1 0 0 1 0 1 write contrast 9.1.12 - 1 1 0 0 ev6 ev5 ev4 ev3 ev2 ev1 ev0 ev = 0 to 127 (28h) dispoff 0 1 0 0 0 1 0 1 0 0 0 display off 9.1.13 (29h) dispon 0 1 0 0 0 1 0 1 0 0 1 display on 9.1.14 (2ah) caset 0 1 0 0 0 1 0 1 0 1 0 column address set 9.1.15 1 1 0 0 xs6 xs5 xs4 xs3 xs2 xs1 xs0 x_adr start: 0 xs 65h 1 1 0 0 xe6 xe5 xe4 xe3 xe2 xe1 xe0 x_adr end: xs xe 65h (2bh) raset 0 1 0 0 0 1 0 1 0 1 1 row address set 9.1.16 1 1 0 0 ys6 ys5 ys4 ys3 ys2 ys1 ys0 y_adr start: 0 ys 5fh 1 1 0 0 ye6 ye5 ye4 ye3 ye2 ye1 ye0 y_adr end: ys ye 5fh (2ch) ramwr 0 1 0 0 0 1 0 1 1 0 0 memory write 9.1.17 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write data
ST7625 ver 1.6 55/160 2008/07 (2eh) ramrd 0 1 0 0 0 1 0 1 1 1 0 memory read 9.1.18 1 1 0 - - - - - - - - dummy read 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 (30h) ptlar 0 1 0 0 0 1 1 0 0 0 0 partial area 9.1.19 1 1 0 -- ps6 ps5 ps4 ps3 ps2 ps1 ps0 1 1 0 -- pe6 pe5 pe4 pe3 pe2 pe1 pe0 (33h) scrlar 0 1 0 0 0 1 1 0 0 1 1 scroll area 9.1.20 - 1 1 0 0 tfa6 tfa5 tfa4 tfa3 tfa2 tfa1 tfa0 tfa= 0~95 - 1 1 0 0 vsa6 vsa5 vsa4 vsa3 vsa2 vsa1 vsa0 vsa= 0~95 - 1 1 0 0 bfa6 bfa5 bfa4 bfa3 bfa2 bfa1 bfa0 bfa= 0~95 (36h) madctr 0 1 0 0 0 1 1 0 1 1 0 memory data access control 9.1.21 - 1 1 0 my mx mv ml rgb - - - - (37h) vscsad 0 1 0 0 0 1 1 0 1 1 1 scroll start address of ram 9.1.22 1 1 0 0 ssa6 ssa5 ssa4 ssa3 ssa2 ssa1 ssa0 ssa = 0~95 (38h) idmoff 0 1 0 0 0 1 1 1 0 0 0 idle mode off 9.1.23 (39h) idmon 0 1 0 0 0 1 1 1 0 0 1 idle mode on 9.1.24 (3ah) colmod 0 1 0 0 0 1 1 1 0 1 0 interface pixel format 9.1.25 - 1 1 0 - - - - - p2 p1 p0 interface format note 1: commands 10h, 12h, 13h, 20h, 21h, 25h, 28h, 29h, 30h, 36h (bit ml only), 38h and 39h are updat ed during v-sync when module is in sleep out mode to avoid abno rmal visual effects. during sleep in mode, these commands are updated im mediately. read status (09h) is updated immediately both in sle ep in mode and sleep out mode.
ST7625 ver 1.6 56/160 2008/07 command table-2 hex command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 function ref (b0h) dutyset 0 1 0 1 0 1 1 0 0 0 0 display duty setting 9.1.26 1 1 0 0 du6 du5 du4 du3 du2 du1 du0 (b1h) firstcom 0 1 0 1 0 1 1 0 0 0 1 first com. page address 9.1.27 1 1 0 -- f6 f5 f4 f3 f2 f1 f0 (b3h) oscdiv 0 1 0 1 0 1 1 0 0 1 1 fosc divider 9.1.28 1 1 0 - - - - - - cld1 cld0 (b5h) nlinvset 0 1 0 1 0 1 1 0 1 0 1 n-line control 9.1.29 1 1 0 m n6 n5 n4 n3 n2 n1 n0 (b7h) segscandir 0 1 0 1 0 1 1 0 1 1 1 seg scan direction for glass layout 9.1.30 1 1 0 0 smx 0 0 sbgr 0 0 0 (b8h) rmwin 0 1 0 1 0 1 1 1 0 0 0 read modify write control in 9.1.31 (b9h) rmwout 0 1 0 1 0 1 1 1 0 0 1 read modify write control out 9.1.32 (c0h) vopset 0 1 0 1 1 0 0 0 0 0 0 vop setting 9.1.33 1 1 0 vop7 vop6 vop5 vop4 vop3 vop2 vop1 vop0 1 1 0 - - - - - - - vop8 (c1h) vopofsetinc 0 1 0 1 1 0 0 0 0 0 1 +40mv/setp 9.1.34 (c2h) vopofsetdec 0 1 0 1 1 0 0 0 0 1 0 -40mv/setp 9.1.35 (c3h) biassel 0 1 0 1 1 0 0 0 0 1 1 bias selection 9.1.36 1 1 0 - - - - - bias2 bias1 bias0 (c4h) bstbmpxsel 0 1 0 1 1 0 0 0 1 0 0 booster setting 9.1.37 1 1 0 - - - - - bst2 bst 1 bst0 (c5h) bsteffsel 0 1 0 1 1 0 0 0 1 0 1 booster efficiency selection 9.1.38 1 1 0 - - - - - - btf1 btf0 (c7h) vopoffset 0 1 0 1 1 0 0 0 1 1 1 vop offset fuse bit adjust 9.1.39 1 1 0 vos7 vos6 vos5 vos4 vos3 vos2 vos1 vos0 1 1 0 - - - - - - - vos8 (cbh) vgsorcsel 0 1 0 1 1 0 0 1 0 1 1 fvg with booster x2 control 9.1.40 1 1 0 - - - - - - - 2bt0
ST7625 ver 1.6 57/160 2008/07 (d0h) anaset 0 1 0 1 1 0 1 0 0 0 0 analog circuit setting 9.1.41 1 1 0 0 0 0 1 1 1 0 1 (d7h) autoloadset 0 1 0 1 1 0 1 0 1 1 1 mask rom data auto re-load control 9.1.42 1 1 0 0 0 0 ard 1 1 1 1 (deh) rdtststatus 0 1 0 1 1 0 1 1 1 1 0 read ic status 9.1.43 1 0 1 - - - - - - - - dummy read 1 0 1 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 otp read control (e0h) epctin 0 1 0 1 1 1 0 0 0 0 0 control otp wr/rd 9.1.44 1 1 0 0 0 ewr 0 0 0 0 0 otp rom write control (e1h) epctout 0 1 0 1 1 1 0 0 0 0 1 otp control cancel 9.1.45 (e2h) epmwr 0 1 0 1 1 1 0 0 0 1 0 write to otp 9.1.46 (e3h) epmrd 0 1 0 1 1 1 0 0 0 1 1 read from otp 9.1.47 (e4h) otpsel 0 1 0 1 1 1 0 0 1 0 0 select otp 9.1.48 1 1 0 ms1 ms0 0 1 1 0 0 0 (e5h) romset 0 1 0 1 1 1 0 0 1 0 1 programmable rom setting 9.1.49 1 1 0 0 0 0 0 1 0 0 1 (ebh) hpmset 0 1 0 1 1 1 0 1 0 1 1 high power mode setting 9.1.50 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 (f0h) frmsel 0 1 0 1 1 1 1 0 0 0 0 frame freq. in temp range a,b,c and d 9.1.51 1 1 0 - - - diva fa3 fa2 fa1 fa0 1 1 0 - - - divb fb3 fb2 fb1 fb0 1 1 0 - - - divc fc3 fc2 fc1 fc0 1 1 0 - - - divd fd3 fd2 fd1 fd0 (f1h) frm8sel 0 1 0 1 1 1 1 0 0 0 1 frame freq. in temp range a,b,c and d (idle) 9 .1.52 1 1 0 - - - f8a4 f8a3 f8a2 f8a1 f8a0 1 1 0 - - - f8b4 f8b3 f8b2 f8b1 f8b0 1 1 0 - - - f8c4 f8c3 f8c2 f8c1 f8c0 1 1 0 - - - f8d4 f8d3 f8d2 f8d1 f8d0 (f2h) tmprng 0 1 0 1 1 1 1 0 0 1 0 temp range a,b and c 9.1.53 1 1 0 - ta6 ta5 ta4 ta3 ta2 ta1 ta0 1 1 0 - tb6 tb5 tb4 tb3 tb2 tb1 tb0 1 1 0 - tc6 tc5 tc4 tc3 tc2 tc1 tc0
ST7625 ver 1.6 58/160 2008/07 (f3h) tmphys 0 1 0 1 1 1 1 0 0 1 1 hysteresis value set 9.1.54 1 1 0 - - - - th3 th2 th1 th0 (f4h) tempsel 0 1 0 1 1 1 1 0 1 0 0 tempsel 9.1.55 1 1 0 mt13 mt12 mt11 mt10 mt03 mt02 mt01 mt00 1 1 0 mt33 mt32 mt31 mt30 mt23 mt22 mt21 mt20 1 1 0 mt53 mt52 mt51 mt50 mt43 mt42 mt41 mt40 1 1 0 mt73 mt72 mt71 mt70 mt63 mt62 mt61 mt60 1 1 0 mt93 mt92 mt91 mt90 mt83 mt82 mt81 mt80 1 1 0 mtb3 mtb2 mtb1 mtb0 mta3 mta2 mta1 mta0 1 1 0 mtd3 mtd2 mtd1 mtd0 mtc3 mtc2 mtc1 mtc0 1 1 0 mtf3 mtf2 mtf1 mtf0 mte3 mte2 mte1 mte0 (f7h) thys 0 1 0 1 1 1 1 0 1 1 1 temperature detection threshold 9.1.56 1 1 0 thys 7 thys 6 thys 5 thys 4 thys 3 thys 2 thys 1 thys 0 (f9h) frame set 0 1 0 1 1 1 1 1 0 0 1 set frame1 rgb value 9.1.57 1 1 0 - - - p14 p13 p12 p11 p10 1 1 0 - - - p24 p23 p22 p21 p20 : : : : : : : : : : : 1 1 0 - - - p154 p153 p152 p151 p150 1 1 0 - - - p164 p163 p162 p161 p160
ST7625 ver 1.6 59/160 2008/07 9.1.1 nop(00h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex nop 0 1 0 0 0 0 0 0 0 0 0 (00h) parameter no parameter description this command is empty command. it does not have eff ect on the display module. however it can be used to terminate ram data write as described in ramwr (memory write) and parameter write commands. restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence n/a s/w reset n/a h/w reset n/a flow chart -
ST7625 ver 1.6 60/160 2008/07 9.1.2 swreset: software reset (01h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex swreset 0 1 0 0 0 0 0 0 0 0 1 (01h) parameter no parameter description when the software reset command is written, it causes a software reset. it resets the commands and parameters to their s/w reset default v alues and all segment & common outputs are set to vm (display off: blank di splay). (see default tables in each command description) note: the frame memory contents are not affected by this command. restriction it will be necessary to wait 5msec before sending new command following software reset. the display module loads all display supplie rs factory default values to the registers during 5msec. if software reset is applied during sleep out mode, it will be necessary to wait 120msec before sending sleep out c ommand. software reset command cannot be sent during sleep ou t sequence. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence n/a s/w reset n/a h/w reset n/a flow chart swreset set command stos/w default value display whole blankscreen sleepinmode command parameter display action mode legend sequential transter
ST7625 ver 1.6 61/160 2008/07 9.1.3 rddst: read display status (09h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex rddst 0 1 0 0 0 0 0 1 0 0 1 (09h) dummy read 1 0 1 - - - - - - - - - 2 nd parameter 1 0 1 st31 st30 st29 st28 st27 st26 st25 st24 - 3 rd parameter 1 0 1 st23 st22 st21 st20 st19 st18 st17 st16 - 4 th parameter 1 0 1 st15 st14 st13 st12 st11 st10 st9 st8 - 5 th parameter 1 0 1 st7 st6 st5 st4 st3 st2 st1 st0 - note: - dont care description this command indicates the current status of the di splay as described in the table below: bit description value st31 booster voltage status 1=booster on, 0=off st30 row address order (my) 1=decrement, 0=increment st29 column address order (mx) 1=decrement, 0=increment st28 row/column order (mv) 1= row/column exchange (mv=1) 0= normal (mv=0) st27 scan address order (ml) 1=decrement, 0=increment st26 rgb/bgr order (rgb) 1=bgr, 0=rgb st25 not used 0 st24 not used 0 st23 not used 0 st22 st21 st20 interface color pixel format definition 010 = 8-bit / pixel, 011 = 12-bit / pixel type a 100 = 12-bit / pixel type b 101 = 16-bit / pixel, 110 = 18-bit / pixel, 111 = 24-bit / pixel st19 idle mode on/off 1 = on, 0 = off st18 partial mode on/off 1 = on, 0 = off st17 sleep in/out 1 = out, 0 = in st16 display normal mode on/off 1 = normal display, 0 = partial display st15 vertical scrolling status 1 = scroll on, 0 = scrol l off st14 not used 0 st13 inversion status 1 = on, 0 = off st12 all pixels on 1 = mode on, 0 = mode off st11 all pixels off 1 = mode on, 0 = mode off st10 display on/off 1 = on, 0 = off st9 internal use -- st8 not used 0 st7 not used 0 st6 not used 0 st5 internal use -- st4 not used 0 st3 not used 0 st2 not used 0 st1 not used 0 st0 not used 0
ST7625 ver 1.6 62/160 2008/07 restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (st31 to st0) power on sequence 0000 0000_0101 0001_0000 0000_0000 0000 s/w reset 0xxx xx00_0xxx 0001_0000 0000_0000 0000 h/w reset 0000 0000_0101 0001_0000 0000_0000 0000 flow chart read 09h read 09h dummy clock dummy read send 2nd parameter send 2nd parameter send 3rd parameter send 3rd parameter send 4th parameter send 4th parameter serial i/f mode parallel i/f mode send 5th parameter sendth parameter command parameter display action mode legend sequential transter
ST7625 ver 1.6 63/160 2008/07 9.1.4 slpin: sleep in (10h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex slpin 0 1 0 0 0 0 1 0 0 0 0 (10h) parameter no parameter description this command causes the lcd module to enter the minim um power consumption mode. in this mode the dc/dc converter is stopped, internal d isplay oscillator is stopped, and panel scanning is stopped. com/segoutput memoryscanoperation dcchargeinthecapacitor lcddrivingvoltage(plus) lcddrivingvoltage(minus) internaloscillator blankdisplay stop(blankdisplay) stop discharge stop 0v 0v 0v mcu interface and memory are still working and the mem ory keeps its contents restriction this command has no effect when module is already in sleep in mode. sleep in mode can only be exit by the sleep out command (11h). it will be necessary to wait 5msec before sending the next command. this is for allowing time to stablilize supply voltages and clock circuits. it will be necessary to wait 120msec after sending sl eep out command (when in sleep in mode) before sleep in command can be sent. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence sleep in mode s/w reset sleep in mode h/w reset sleep in mode
ST7625 ver 1.6 64/160 2008/07 flow chart it takes about 120 msec to get into sleep in mode ( booster off state) after slpin command issued. the results of booster off can be check by rddst (09h) command bit31. slpin display whole blank screen (automatic no effect to disp on/off commands) drain charge from lcd panel stop dc-dc converte r stop internal oscillator sleep in mode command parameter display action mode legend sequential transter
ST7625 ver 1.6 65/160 2008/07 9.1.5 slpout: sleep out (11h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex slpout 0 1 0 0 0 0 1 0 0 0 1 (11h) parameter no parameter description this command turns off sleep mode. in this mode the dc/dc converter is enabled, internal display oscillator is started, and panel scanning i s started. com/segoutput memoryscanoperation dcchargeinthecapacitor lcddrivingvoltage(plus) lcddrivingvoltage(minus) internaloscillator charge 0v 0v 0v memorycontents stop(blankdisplay) stop (ifdispon29hisset) restriction this command has no effect when module is already in sleep out mode. sleep out mode can only be exit by the sleep in command (10h). it will be necessary to wait 5msec before sending the next command. this is for allowing time to stablilize supply voltages and clock circuits. the display module loads all display suppliers fac tory default values to the registers during this 5msec and there cannot be any abnormal visual effec t on the display image if factory default and register values are same when this load is done and when the display module is already sleep out Cmode. it will be necessary to wait 120msec after sending sl eep in command (when in sleep out mode) before sleep out command can be sent. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence sleep in mode s/w reset sleep in mode h/w reset sleep in mode
ST7625 ver 1.6 66/160 2008/07 flow chart it takes 120msec to become sleep out mode (booster on mode) after slpout command issued. the results of booster on can be check by rdds t (09h) command bit31. slpout start internal oscillator start up dc:dc converter display whole blank screen for 2 firames (automatic no effect to disp on/off commands) display memory contents in accordance with the current command table settings sleep out mode charge offset voltage for lcd panel command parameter display action mode legend sequential transter
ST7625 ver 1.6 67/160 2008/07 9.1.6 ptlon: partial display mode on (12h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex ptlon 0 1 0 0 0 0 1 0 0 1 0 (12h) parameter no parameter description this command turns on partial mode. the partial mod e window is described by the partial area command (30h) exit from ptlon by normal display mode on command (13h) there is no abnormal visual effect during mode chan ge between normal mode on <-> partial mode on. restriction this command has no effect when partial mode is acti ve. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence partial mode off s/w reset partial mode off h/w reset partial mode off flow chart see partial area (30h)
ST7625 ver 1.6 68/160 2008/07 9.1.7 noron: normal display mode on (13h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex noron 0 1 0 0 0 0 1 0 0 1 1 (13h) parameter no parameter description this command returns the display to normal mode. normal display mode on means partial mode off, scrol l mode off. exit from noron by the partial mode on command (12h) there is no abnormal visual effect during mode chan ge between normal mode on <-> partial mode on. restriction this command has no effect when normal display mode is active. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence normal mode on s/w reset normal mode on h/w reset normal mode on flow chart see partial area and vertical scrolling definition desc riptions for details of when to use this command
ST7625 ver 1.6 69/160 2008/07 9.1.8 invoff: display inversion off (20h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex invoff 0 1 0 0 0 1 0 0 0 0 0 (20h) parameter no parameter description this command is used to recover from display invers ion mode. this command makes no change of contents of frame m emory. this command does not change any other status. memory display (example) restriction this command has no effect when module is already in version off mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence display inversion off s/w reset display inversion off h/w reset display inversion off flow chart display inversion on mode invoff display inversion off mode command parameter display action mode legend sequential transter
ST7625 ver 1.6 70/160 2008/07 9.1.9 invon: display inversion on (21h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex invon 0 1 0 0 0 1 0 0 0 0 1 (21h) parameter no parameter description this command is used to enter into display inversio n mode this command makes no change of contents of frame m emory. this command does not change any other status. to exit from display inversion on, the display invers ion off command (20h) should be written. memory display (example) restriction this command has no effect when module is already in version on mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence display inversion off s/w reset display inversion off h/w reset display inversion off flow chart display inversion off mode invon display inversion on mode command parameter display action mode legend sequential transter
ST7625 ver 1.6 71/160 2008/07 9.1.10 apoff: all pixels off (22h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex apoff 0 1 0 0 0 1 0 0 0 1 0 (22h) parameter no parameter description this command is only used for test purpose e.g. pix el response time (on/off) measurements on the passive matrix display. therefore, it is possible t hat this command is not used for final product software. all driver outputs become low data state and displ ay becomes black. this command makes no change of contents of display memory. this command does not change any other status. exit commands are all pixels on, normal display m ode on and partial display on. the display is showing the contents of the frame me mory after normal display mode on and partial display on commands. memory display (example) restriction this command has no effect when module is already al l pixel off mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence all pixel off mode disable s/w reset all pixel off mode disable h/w reset all pixel off mode disable
ST7625 ver 1.6 72/160 2008/07 flow chart normal display mode on allpoff all pixels off mode command parameter display action mode legend sequential transter
ST7625 ver 1.6 73/160 2008/07 9.1.11 apon: all pixels on (23h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex apon 0 1 0 0 0 1 0 0 0 1 1 (23h) parameter no parameter description this command is only used for test purpose e.g. pix el response time (on/off) measurements on the passive matrix display. therefore, it is possible t hat this command is not used for final product software. all driver outputs become high data state and disp lay becomes white. this command makes no change of contents of display memory. this command does not change any other status. exit commands are all pixels on, normal display m ode on and partial display on. the display is showing the contents of the frame me mory after normal display mode on and partial display on commands. memory display (example) restriction this command has no effect when module is already al l pixel on mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence all pixel on mode disable s/w reset all pixel on mode disable h/w reset all pixel on mode disable flow chart
ST7625 ver 1.6 74/160 2008/07 9.1.12 wrcntr: write contrast (25h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex wrcntr 0 1 0 0 0 1 0 0 1 0 1 (25h) parameter 1 1 0 ev6 ev5 ev4 ev3 ev2 ev1 ev0 description this command is used to fine tuning the contrast of the current display. this contrast values can affect segment and common outputs. parameter range: 0-127dec. msb is ev6 and lsb is ev0. default value: 63dec (3fh) restriction - register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence 3fh s/w reset 3fh h/w reset 3fh flow chart
ST7625 ver 1.6 75/160 2008/07 9.1.13 dispoff: display off (28h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex dispoff 0 1 0 0 0 1 0 1 0 0 0 (28h) parameter no parameter description this command is used to enter into display off mode. in this mode, the output from frame memory is disables and blank page inserted. this command makes no change of contents of frame m emory. this command does not change any other status. there will be no abnormal visible effect on the disp lay. exit from this command by display on (29h) memory display (example) restriction this command has no effect when module is already in display off mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence display off s/w reset display off h/w reset display off flow chart display on mode dispoff display off mode command parameter display action mode legend sequential transter
ST7625 ver 1.6 76/160 2008/07 9.1.14 dispon: display on (29h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex dispon 0 1 0 0 0 1 0 1 0 0 1 (29h) parameter no parameter description turn on the display screen according to the current display data ram content and the display timing and setting. this command is used to recover from display off mod e. output from the frame memory is enabled. this command makes no change of contents of frame m emory. this command does not change any other status. memory display (example) restriction this command has no effect when module is already in display on mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence display off s/w reset display off h/w reset display off flow chart display off mode dispon display on mode command parameter display action mode legend sequential transter
ST7625 ver 1.6 77/160 2008/07 9.1.15 caset: column address set (2ah) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex caset 0 1 0 0 0 1 0 1 0 1 0 (2ah) 1 st parameter 1 1 0 - xs6 xs5 xs4 xs3 xs2 xs1 xs0 2 nd parameter 1 1 0 - xe6 xe5 xe4 xe3 xe2 xe1 xe0 note: - dont care description this command is used to define area of frame memory where mcu can access. this command makes no change on the other driver st atus. the value of xs [6:0] and xe [6:0] are referred when ramwr command comes. each value represents one column line in the frame memory. restriction xs [6:0] always must be equal to or less than xe [6: 0] when xs [6:0] or xe [6:0] is greater than 65h (when mv=0) or 5fh (when mv=1), data of out of range will be ignored. (parameter range: 0 xs [7:0] xe [7:0] 101(65h)) : mv=0 (parameter range: 0 xs [7:0] xe [7:0] 95(5fh) : mv=1 register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status xs [6:0] xe [6:0] (mv=0) xe [6:0] (mv=1) power on sequence 00h (00d) 65h (101d) s/w reset 00h (00d) 65h (101d) 5fh (95d) h/w reset 00h (00d) 65h (101d)
ST7625 ver 1.6 78/160 2008/07 flow chart caset 1st parameter xs[6:0] 2nd parameter xe[6:0] paset 1st parameter ys[6:0] 2nd parameter ye[6:0] ramwr image data d1[7:0],d2[7:0] .dn[7:0] any command command parameter display action mode legend sequential transter
ST7625 ver 1.6 79/160 2008/07 9.1.16 raset: row address set (2bh) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex raset 0 1 0 0 0 1 0 1 0 1 1 (2bh) 1 st parameter 1 1 0 - ys6 ys5 ys4 ys3 ys2 ys1 ys0 2 nd parameter 1 1 0 - ye6 ye5 ye4 ye3 ye2 ye1 ye0 note: - dont care description this command is used to define area of frame memory where mcu can access. this command makes no change on the other driver st atus. the value of ys [6:0] and ye [6:0] are referred when ramwr command comes. each value represents one column line in the frame memory. (example) ys[6:0] ye[6:0] restriction ys [6:0] always must be equal to or less than ye [6: 0] when ys [6:0] or ye [6:0] is greater than 5fh (when mv=0) or 65h (when mv=1), data of out of range will be ignored. (parameter range: 0 ys [6:0] ye [6:0] 95 (5fh)) : mv = 0 (parameter range: 0 ys [6:0] ye [6:0] 101 (65h)) : mv = 1 register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status ys [6:0] ye [6:0] (mv=0) ye [6:0] (mv=1) power on sequence 00h (00d) 5fh (95d) s/w reset 00h (00d) 5fh (95d) 65h (101d) h/w reset 00h (00d) 5fh (95d)
ST7625 ver 1.6 80/160 2008/07 flow chart caset 1st parameter xs[6:0] 2nd parameter xe[6:0] paset 1st parameter ys[6:0] 2nd parameter ye[6:0] ramwr image data d1[7:0],d2[7:0] .dn[7:0] any command command parameter display action mode legend sequential transter
ST7625 ver 1.6 81/160 2008/07 9.1.17 ramwr: memory write (2ch) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex ramwr 0 1 0 0 0 1 0 1 1 0 0 (2ch) write data 1 d1[7:0] 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 - : 1 1 0 : : : : : : : : - write data n dn[7:0] 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 - description this command is used to transfer data mcu to frame me mory. this command makes no change to the other driver st atus. when this command is accepted, the column register and the row register are reset to the start column/start row positions. the start column/start row positions are different in accordance with madctr setting. then d [7:0] is stored in frame memory and the column regi ster and the row register incremented as in figure 7.3. frame write can be canceled by sending any other co mmand. restriction in all color modes, there is no restriction on leng th of parameters. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence contents of memory is set randomly s/w reset contents of memory is remained h/w reset contents of memory is remained flow chart command parameter display action mode legend sequential transter ramwr image data d1[7:0],d2[7:0] .dn[7:0] any command
ST7625 ver 1.6 82/160 2008/07 9.1.18 ramrd : memeory read (2eh) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex ramrd 0 1 0 0 0 1 0 1 1 0 0 (2eh) dummy read 1 0 1 x x x x x x x x x read data 1 d1[7:0] 1 0 1 d7 d6 d5 d4 d3 d2 d1 d0 00h ~ ffh 1 0 1 dx7 dx6 dx5 dx4 dx3 dx2 dx1 dx0 00h ~ ffh read data n dn[7:0] 1 0 1 dn7 dn6 dn5 dn4 dn3 dn2 dn1 dn0 00h ~ ffh description this command is used to transfer data from frame me mory to mcu. when this command is accepted, the column register and the page register are reset to the start column/start page positions. the start column/start page positions are different in accordance with madctr setting. then d[7:0] is read back from the frame mem ory and the column register and the page register incremented. frame read can be stopped by s ending any other command. restriction in all color modes, the frame read is always 16bit so there is no restriction on length of parameters. note: memory read is only possible via t he parallel interface. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in or booster off yes default status default value power on sequence contents of memory is set randomly s/w reset contents of memory is not cleared h/w reset contents of memory is not cleared flow chart
ST7625 ver 1.6 83/160 2008/07 9.1.19 ptlar: partial area (30h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex ptlar 0 1 0 0 0 1 1 0 0 0 0 (30h) 1 st parameter 1 1 0 - ps6 ps5 ps4 ps3 ps2 ps1 ps0 - 2 nd parameter 1 1 0 - pe6 pe5 pe4 pe3 pe2 pe1 pe0 - note: - dont care description this command defines the partial modes display are a. there are 2 parameters associated with this command, the first defines the start line (ps) and the second the end line (pe), as illustrated in the figures below. psl and pel refer to the frame memory line counter. if end line > start line when madctr ml=0: if end line > start line when madctr ml=1: if end line < start line when madctr ml=0: * row1: frame memory row address 1. if end line = start line then the partial area will be one line deep. restriction psl[6:0] and pel[6:0] is based on line unit. psl[6:0]=00h, 01h, 02h, 03h, , 5fh
ST7625 ver 1.6 84/160 2008/07 pel[6:0]= 00h, 01h, 02h, 03h, , 5fh register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status psl [6:0] pel [6:0] power on sequence 00h (00d) 5fh (95d) s/w reset 00h (00d) 5fh (95d) h/w reset 00h (00d) 5fh (95d) flow chart
ST7625 ver 1.6 85/160 2008/07 9.1.20 scrlar: scroll area (33h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex scrlar 0 1 0 0 0 1 1 0 0 1 1 (33h) 1 st parameter 1 1 0 - tfa6 tfa5 tfa4 tfa3 tfa2 tfa1 tfa0 - 2 nd parameter 1 1 0 - vsa6 vsa5 vsa4 vsa3 vsa2 vsa1 vsa0 - 3 rd parameter 1 1 0 - bfa6 bfa5 bfa4 bfa3 bfa2 bfa1 bfa0 - note: - dont care description this command just defines the vertical scrolling ar ea of the display and not performs vertical scroll. when madctr bl=0 the 1 st parameter tfa [6:0] describes the top fixed area (i n no. of lines from top of the frame memory and display). the 2 nd parameter vsa [6:0] describes the height of the ver tical scrolling area (in no. of lines of the frame memory [not the display] from the vertica l scrolling start address) the first line appears immediately after the bottom most line of the top f ixed area. the 3 rd parameter bfa [6:0] describes the bottom fixed area (in no. of lines from bottom of the frame memory and display). tfa, vsa and bfa refer to the frame memory line poi nter. restriction the condition is (tfa+vsa+bfa) = 96, otherwise scrol ling mode is undefined. in vertical scroll mode, madctr parameter mv should b e set to 0-this only affects the frame memory write. tfa[6:0], vsa[6:0] and bfa[6:0] is based on line un it. tfa[6:0]= 00h, 01h, 02h, 03h, , 5fh vsa[6:0]= 00h, 01h, 02h, 03h, , 5fh bfa[6:0]= 00h, 01h, 02h, 03h, , 5fh register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status tfa [6:0] vsa [6:0] bfa [6:0] power on sequence 00h 5fh (95d) 00h s/w reset 00h 5fh (95d) 00h h/w reset 00h 5fh (95d) 00h
ST7625 ver 1.6 86/160 2008/07 flow chart 1.toenterverticalscrollmode: command parameter display action mode legend sequential transter normalmode scrlar 1stparametertfa[6:0] 2ndparametervsa[6:0] 3rdparameterbfa[6:0] caset 1stparameterxs[6:0] 2ndparameterxe[6:0] raset madctr parameter ramwr scrollvideodata vscsad 1stparameterssa[6:0] scrollmode 1stparameterys[6:0] 2ndparameterye[6:0] onlyrequired fornonrolling scrolling redefinesthe framememory windowthat thescrolldata willbewritten to. optionalit maybe necessaryto redefinethe framememory writedirection. note: the frame memory window size must be defined co rrectly otherwise undesirable image will be displayed.
ST7625 ver 1.6 87/160 2008/07 flow chart 2.continuousscroll: command parameter display action mode legend sequential transter normalmode caset 1stparameterxs[6:0] 2ndparameterxe[6:0] raset ramwr scrollvideodata vscsad 1stparameterssa[6:0] 1stparameterys[6:0] 2ndparameterye[6:0] onlyrequired fornonrolling scrolling scrollmode dispoff noron/ptlon scrollmodeoff ramwr videodatad1[7:0], d2[7:0]...dn[7:0] dispon 3.toexitverticalscrollmode: canbeskipped note: scroll mode can be exit by both the normal displ ay mode on(13h) and partial mode on (12h) commands.
ST7625 ver 1.6 88/160 2008/07 9.1.21 madctr: memory data access control (36h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex madctr 0 1 0 0 0 1 1 0 1 1 0 (36h) parameter 1 1 0 my mx mv ml rgb - - - - note: - dont care description this command defines read/write scanning direction of frame memory. this command makes no change on the other driver st atus. note: ml affects to partial area (30h), vertical scr olling definition (33h), vertical scrolling start address (37h), partial on (12h) commands bit assignment bit name description my row address order mx column address order mv row/column order these 3bits controls mcu to memory write/read direc tion. (see section 7.3.2 mcu to memory write/read direct ion) ml line address order lcd refresh direction control rgb rgb-bgr order color selector switch control 0=rgb color filter panel, 1=bgr color filter panel) the contents of the frame memory are not changed. restriction d2, d1 and d0 of the 1 st parameter are set to 000internally. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence my=0,mx=0,mv=0,ml=0,rgb=0 s/w reset not changed h/w reset my=0,mx=0,mv=0,ml=0,rgb=0
ST7625 ver 1.6 89/160 2008/07 flow chart command parameter display action mode legend sequential transter madctl 1st parameter b[7:0]
ST7625 ver 1.6 90/160 2008/07 9.1.22 vscsad: vertical scroll start address of ram (37h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex vscsad 0 1 0 0 0 1 1 0 1 1 1 (37h) parameter 1 1 0 - ssa6 ssa5 ssa4 ssa3 ssa2 ssa1 ssa0 note: - dont care description this command is used together with vertical scrollin g definition (33h). these two commands describe the scrolling area and the scrolling mode. the vertical scrolling start address command has on e parameter which describes which line in the frame memory will be written as the first line af ter the last line of the top fixed area on the display as illustrated below: this command start the scrolling. exit from v-scrolling mode by commands partial mode on (12h) or normal mode on (13h). note: when new pointer position and picture data are s ent, the result on the display will happen at the next panel scan to avoid tearing effe ct. ssa refers to the frame memory line pointer restriction since the value of the vertical scrolling start add ress is absolute (with reference to the frame memory), it must not enter the fixed area (defined by vertical scrolling definition (33h)-otherwise undesirable image will be displayed o n the panel. ssa [6:0] is based on line unit. ssa [6:0] = 00h, 01h, 02h, 03h, , 5fh register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out no partial mode on, idle mode on, sleep out no sleep in yes default status default value power on sequence 00 s/w reset 00 h/w reset 00 flow chart see vertical scrolling definition (33h) description.
ST7625 ver 1.6 91/160 2008/07 9.1.23 idmoff: idle mode off (38h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex idmoff 0 1 0 0 0 1 1 1 0 0 0 (38h) parameter no parameter description this command is used to recover from idle mode on. there will be no abnormal visible effect on the disp lay mode change transition. in the idle off mode, 1. lcd can display maximum 65536 colors. 2. normal frame frequency is applied. restriction this command has no effect when module is already in idle off mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence idle mode off s/w reset idle mode off h/w reset idle mode off flow chart
ST7625 ver 1.6 92/160 2008/07 9.1.24 idmon: idle mode on (39h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex idmon 0 1 0 0 0 1 1 1 0 0 1 (39h) parameter no parameter description this command is used to enter into idle mode on. there will be no abnormal visible effect on the disp lay mode change transition. in the idle on mode, 1. color expression is reduced. the primary and the secondary colors using msb of each r, g and b in the frame memory, 8 color depth data i s displayed. 2. 8-color mode frame frequency is applied. 3. exit from idmon by idle mode off (38h) command x: dont care color r 4 r 3 r 2 r 1 r 0 g 5 g 4 g 3 g 2 g 1 g 0 b 4 b 3 b 2 b 1 b 0 black 0xxxx 0xxxxx 0xxxx blue 0xxxx 0xxxxx 1xxxx red 1xxxx 0xxxxx 0xxxx magenta 1xxxx 0xxxxx 1xxxx green 0xxxx 1xxxxx 0xxxx cyan 0xxxx 1xxxxx 1xxxx yellow 1xxxx 1xxxxx 0xxxx white 1xxxx 1xxxxx 1xxxx restriction this command has no effect when module is already in idle on mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence idle mode off s/w reset idle mode off h/w reset idle mode off
ST7625 ver 1.6 93/160 2008/07 flow chart command parameter display action mode legend sequential transter idle off mode idmon idle on mode
ST7625 ver 1.6 94/160 2008/07 9.1.25 colmod: interface pixel format (3ah) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex colmod 0 1 0 0 0 1 1 1 0 1 0 (3ah) parameter 1 1 0 - - - - - p2 p1 p0 - description this command is used to define the format of rgb pic ture data, which is to be transferred via the mcu interface. the formats are shown in the table: interface format p2 p1 p0 not defined 0 0 0 not defined 0 0 1 8bit/ pixel /256 0 1 0 12bit/pixel /4k (type a) 0 1 1 12bit/pixel /4k (type b) 1 0 0 16bit/pixel/65k 1 0 1 18bit/pixel/262k 1 1 0 24bit/pixel/16m 1 1 1 restriction there is no visible effect until the frame memory i s written to. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence 05h (16bit/pixel/65k) s/w reset no change h/w reset 05h (16bit/pixel/65k) flow chart command parameter display action mode legend sequential transter 16 bit/pixel mode colmod 011 12 bit/pixel mode
ST7625 ver 1.6 95/160 2008/07 9.1.26 dutyset: display duty setting (b0h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex dutyset 0 1 0 1 0 1 1 0 0 0 0 (b0h) parameter 1 1 0 0 du6 du5 du4 du3 du2 du1 du0 - note: - dont care description this command is used to set display duty. command se t = display duty numbers - 1. example: duty du6 du5 du4 du3 du2 du1 du0 command set= display duty numbers-1 example: 1/96 duty 1 0 1 1 1 1 1 96-1=95 restriction display duty must > 4 (1/4 duty) register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (du[6:0]) power on sequence 01011101b (5fh) s/w reset 01011101b (5fh) h/w reset 01011111b (5fh) flow chart
ST7625 ver 1.6 96/160 2008/07 9.1.27 firstcom: first com. page address (b1h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex firstcom 0 1 0 1 0 1 1 0 0 0 1 (b1h) parameter 1 1 0 -- f6 f5 f4 f3 f2 f1 f0 - note: - dont care description this command defines the first output com number th at mapping to the ram page address 0. for detail setting value, please see the table as below. f6 f5 f4 f3 f2 f1 f0 line address 0 0 0 0 : : 0 0 0 0 0 0 : : 1 1 0 0 0 1 : : 0 2 0 0 0 1 : : 1 3 : : : : : : : : 1 0 1 1 1 1 1 95 example: if firstcom=8, common 8 would output the data of ra m page address 0. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (f[6:0]) power on sequence 00h s/w reset 00h h/w reset 00h flow chart
ST7625 ver 1.6 97/160 2008/07 9.1.28 oscdiv: fosc divider (b3h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex oscdiv 0 1 0 1 0 1 1 0 0 1 1 (b3h) parameter 1 1 0 - - - - - - cld1 cld0 - note: - dont care description this command is used to specify the cl dividing rat io. cld1, cld0: cl dividing ratio. they are used to cha nge number of dividing stages of external or internal clock. cld1 cld0 cl dividing ratio 0 0 0 1 1 0 1 1 not divide 2 divisions 4 divisions 8 divisions restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (cld[0:1]) power on sequence 00b s/w reset 00b h/w reset 00b flow chart
ST7625 ver 1.6 98/160 2008/07 9.1.29 nlinvset: n-line control (b5h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex nlinvset 0 1 0 1 0 1 1 0 1 0 1 (b5h) parameter 1 1 0 m n6 n5 n4 n3 n2 n1 n0 - note: - dont care description this command is used to set the inverted line numbe r with range of 2 to (duty-1) to improve display quality. when m=0, inversion occurs in ever y frame; when m=1, inversion is independent from frames. if n[6:0]=0, n-line inversi on function is disable. line inversion numbers=n[6:0] +1. example: if n[6:0]=7, inversion occurs per 8 line. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status m n[6:0] power on sequence 0b 0000000b s/w reset 0b 0000000b h/w reset 0b 0000000b flow chart
ST7625 ver 1.6 99/160 2008/07 9.1.30 segscandir: seg scan direction for glass lay out (b7h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex comscandir 0 1 0 1 0 1 1 0 1 1 1 (b7h) parameter 1 1 0 0 smx 0 0 sbgr 0 0 0 - note: - dont care description function 0 1 smx inverse the mx setting keep mx inverse mx sbgr inverse the bgr setting keep bgr inverse bgr seg0 05 com94 com95 seg3 com92 com93 com0 com2 com3 com1 common scan direction configuration restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (csd[1:0]) power on sequence 00b s/w reset 00b h/w reset 00b
ST7625 ver 1.6 100/160 2008/07 flow chart
ST7625 ver 1.6 101/160 2008/07 9.1.31 rmwin: read modify write control in(b8h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex rmwin 0 1 0 1 0 1 1 1 0 0 0 (b8h) parameter no parameter note: - dont care description read modify write control in restriction can only be used in 65k color mode. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence -- s/w reset -- h/w reset --
ST7625 ver 1.6 102/160 2008/07 9.1.32 rmwout: read modify write control out(b9h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex rmwout 0 1 0 1 0 1 1 1 0 0 1 (b9h) parameter no parameter note: - dont care description read modify write control out restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence -- s/w reset -- h/w reset --
ST7625 ver 1.6 103/160 2008/07 9.1.33 vopset: vop set (c0h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex vopset 0 1 0 1 1 0 0 0 0 0 0 (c0h) 1 st parameter 1 1 0 vop7 vop6 vop5 vop4 vop3 vop2 vop1 vop0 - 2 nd parameter 1 1 0 - - - - - - - vop8 note: - dont care description the command is used to program the optimum lcd supply voltage v0. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (vop=12v) vop8 vop[7:0] power on sequence 0 11010010b (d2h) s/w reset 0 11010010b (d2h) h/w reset 0 11010010b (d2h) flow chart
ST7625 ver 1.6 104/160 2008/07 9.1.34 vopofsetinc: vop increase 1 (c1h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex vopofsetinc 0 1 0 1 1 0 0 0 0 0 1 (c1h) note: - dont care description with the vopofsetinc and vopofsetdec command the vlc d voltage and therewith the contrast of the lcd can be adjusted. this command increases th e value of vop offset register by 1. if you set the electronic control value to 1111111, the control value is set to 0000000 after this command has been executed. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence -- s/w reset -- h/w reset -- flow chart
ST7625 ver 1.6 105/160 2008/07 9.1.35 vopofsetdec: vop decrease 1 (c2h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex vopofsetdec 0 1 0 1 1 0 0 0 0 1 0 (c2h) note: - dont care description with the vopofsetinc and vopofsetdec command the v lcd voltage and therewith the contrast of the lcd can be adjusted. this command decreases the value of vop offset regi ster by 1. if you set the electronic control value to 0000000, the control value is set to 1111111 after this command has been executed. electronic control value decimal equivalent v0 offset 0111111 63 +2520 mv 0111110 62 +2480 mv 0111101 61 +2440 mv 0000010 2 +80 mv 0000001 1 +40 mv 0000000 0 0 mv 1111111 -1 -40 mv 1111110 -2 -80 mv 1000010 -62 -2480 mv 1000001 -63 -2520 mv 1000000 -64 -2560mv table 9.1.1 possible vop[6:0] values restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence -- s/w reset -- h/w reset --
ST7625 ver 1.6 106/160 2008/07 flow chart
ST7625 ver 1.6 107/160 2008/07 9.1.36 biassel: bias selection(c3h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex biassel 0 1 0 1 1 0 0 0 0 1 1 (c3h) parameter 1 1 0 - - - - - bias2 bias1 bias0 - note: - dont care description select lcd bias ratio of the voltage required for dri ving the lcd. bais2 bais1 bais0 lcd bias 0 0 0 1/12 0 0 1 1/11 0 1 0 1/10 0 1 1 1/9 1 0 0 1/8 1 0 1 1/7 1 1 0 1/6 1 1 1 1/5 restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (bias[2:0]) power on sequence 110b s/w reset 110b h/w reset 110b flow chart
ST7625 ver 1.6 108/160 2008/07 9.1.37 bstpmpxsel: booster set (c4h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex bstpmpxsel 0 1 0 1 1 0 0 0 1 0 0 (c4h) parameter 1 1 0 - - - - - bst2 bst 1 bst0 - note: - dont care description booster setting bst2 bst1 bst0 0 0 0 x1 boosting circuit (booster off) 0 0 1 x2 boosting circuit 0 1 0 x3 boosting circuit 0 1 1 x4 boosting circuit 1 0 0 x5 boosting circuit 1 0 1 x6 boosting circuit 1 1 0 x7 boosting circuit 1 1 1 x8 boosting circuit restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (bst[2:0]) power on sequence 111b s/w reset 111b h/w reset 111b flow chart
ST7625 ver 1.6 109/160 2008/07 9.1.38 bsteffsel: booster efficiency selection (c5h ) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex bsteffsel 0 1 0 1 1 0 0 0 1 0 1 (c5h) parameter 1 1 0 - - - - - - btf1 btf0 - note: - dont care description booster efficiency set btf1 btf0 frequency ( hz ) 0 0 level 1 0 1 level 2 (default) 1 0 level 3 by booster stages (2x, 3x, 4x, 5x, 6x, 7x, 8x) and boo ster efficiency (level1~3) commands, we could easily set the best booster performance with s uitable current consumption. if the booster efficiency is set to higher level (level3 is higher than level1). the boost efficiency is better than lo wer level, and it needs a few more power consumption cu rrent. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (btf[1:0]) power on sequence 01b s/w reset 01b h/w reset 01b flow chart
ST7625 ver 1.6 110/160 2008/07 9.1.39 vopoffset: vop offset fuse bit adjust(c7h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex vopoffset 0 1 0 1 1 0 0 0 1 1 1 (c7h) parameter1 1 1 0 vos7 vos6 vos5 vos4 vos3 vos2 vos1 vos0 - parameter2 1 1 0 - - - - - - - vos8 - note: - dont care description the command is used to the vop offset for v0. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value vos8 vos[7:0] power on sequence 0 0 s/w reset 0 0 h/w reset 0 0 flow chart
ST7625 ver 1.6 111/160 2008/07 9.1.40 vgsorcsel: fvg with bst2x control(cbh) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex vgsorcsel 0 1 0 1 1 0 0 1 0 1 1 (cbh) parameter 1 1 0 - - - - - - - 2bt0 - note: - dont care description 2bt0=0: vg source comes from vdd2 ; 2bt0=1: vg source comes from 2-times charge pump. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (2bt0) power on sequence 1 s/w reset 1 h/w reset 1 flow chart
ST7625 ver 1.6 112/160 2008/07 9.1.41 anaset: analog circuit setting (d0h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex autoloadset 0 1 0 1 1 0 1 0 0 0 0 (d0h) parameter 1 1 0 0 0 0 1 1 1 0 1 - note: - dont care description analog circuit setting. such as follower selection, level shifter power selection. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence 1dh s/w reset 1dh h/w reset 1dh flow chart
ST7625 ver 1.6 113/160 2008/07 9.1.42 autoloadset : mask rom data auto re-load con trol(d7h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex autoloadset 0 1 0 1 1 0 1 0 1 1 1 (d7h) parameter 1 1 0 0 0 0 ard 1 1 1 1 - note: - dont care description mask rom data auto re-load control ard : otp auto recovery enable control, 1: disable ot p auto recovery, 0: enable otp auto recovery restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value ard power on sequence 0 s/w reset 0 h/w reset 0 flow chart
ST7625 ver 1.6 114/160 2008/07 9.1.43 rdtststatus : read ic status(deh) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex rdtststatus 0 1 0 1 1 0 1 1 1 1 0 (deh) dummy read 1 0 1 - - - - - - - - parameter 1 0 1 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 - note: - dont care description read ic status. contect of otp/ rda / pwr_vop read control (selection byte by stusoutbytesel[3:0] control) restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence - s/w reset - h/w reset - flow chart
ST7625 ver 1.6 115/160 2008/07 9.1.44 epctin: control otp wr/rd(e0h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex epctin 0 1 0 1 1 1 0 0 0 0 0 (e0h) parameter 1 1 0 0 0 ewr 0 0 0 0 0 - note: - dont care description ewr: when setting 1 the write enable of otp will be opened. ewr: when setting 0 the read enable of otp will be opened. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (wr/xrd) power on sequence 0 s/w reset 0 h/w reset 0 flow chart
ST7625 ver 1.6 116/160 2008/07 9.1.45 epcout: otp control cancel(e1h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex epcout 0 1 0 1 1 1 0 0 0 0 1 (e1h) note: - dont care description ic exits the otp control circuit when executing this command. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence -- s/w reset -- h/w reset -- flow chart
ST7625 ver 1.6 117/160 2008/07 9.1.46 epmwr: write to otp(e2h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex epcout 0 1 0 1 1 1 0 0 0 1 0 (e2h) note: - dont care description ic actives trigger to start otp programming when exec uting this command. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence -- s/w reset -- h/w reset -- flow chart
ST7625 ver 1.6 118/160 2008/07 9.1.47 epmrd: read from otp(e3h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex epmrd 0 1 0 1 1 1 0 0 0 1 1 (e3h) note: - dont care description ic actives trigger to start otp data download to circ uit when executing this command. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence s/w reset h/w reset flow chart
ST7625 ver 1.6 119/160 2008/07 9.1.48 otpsel: sel otp(e4h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex otpsel 0 1 0 1 1 1 0 0 1 0 0 (e4h) parameter 1 1 0 ms1 ms0 0 1 1 0 0 0 - note: - dont care description this command defines otp selection for eeprom contro l. please see the table as below: ms1 ms0 mode 0 0 disable 0 1 otp 1 0 disable restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (ms[1:0]) power on sequence 00 s/w reset 00 h/w reset 00 flow chart
ST7625 ver 1.6 120/160 2008/07 9.1.49 romset: programmable rom setting(e5h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex otpsel 0 1 0 1 1 1 0 0 1 0 1 (e5h) parameter 1 1 0 0 0 0 0 1 0 0 1 - note: - dont care description set the otp writing timing. value 0x09 is the best value for ST7625 restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value (ms[1:0]) power on sequence 0f s/w reset 0f h/w reset 0f flow chart
ST7625 ver 1.6 121/160 2008/07 9.1.50 hpmset : high power mode setting (ebh) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 1 1 1 0 1 0 1 1 ebh 1 st parameter 1 1 0 0 0 0 0 0 0 0 1 2 nd parameter 1 1 0 0 0 0 0 0 0 0 0 description high power mode for volatage compensation. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status 1 st paramter 2 nd parameter power on sequence 00h 00h s/w reset 00h 00h h/w reset 00h 00h flow chart 1st parameter : 01h 2nd parameter : 00h hpmsel
ST7625 ver 1.6 122/160 2008/07 9.1.51 frmsel: frame freq. in temp. range (f0h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 1 1 1 1 0 0 0 0 f0h 1 st parameter 1 1 0 - - - diva fa3 fa2 fa1 fa0 range a 2 nd parameter 1 1 0 - - - divb fb3 fb2 fb1 fb0 range b 3 rd parameter 1 1 0 - - - divc fc3 fc2 fc1 fc0 range c 4 th parameter 1 1 0 - - - divd fd3 fd2 fd1 fd0 range d description select frame freq. in normal display mode. 1 st parameter : frame freq. value set in temperature r ange 30(-30 ) to ta 2 nd parameter : frame freq. value set in temperature p range ta to tb 3 rd parameter : frame freq. value set in temperature r ange tb to tc 4 th parameter : frame freq. value set in temperature r ange tc to 145(90 ) for command setting to frame rate value look-up-tab le, please see the following table: divx fx[3:0] (hex) frame rate (hz) 0 75 1 76 2 77 3 80 4 84 5 88 6 92 7 97 8 102 9 108 a 115 b 123 c 133 d 144 e 155 1 f 170 0 0~f (frame rate)/2 restriction
ST7625 ver 1.6 123/160 2008/07 register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status fa[4:0] fb[4:0] fc[4:0] fd[4:0] power on sequence 06h 0bh 0dh 12h s/w reset 06h 0bh 0dh 12h h/w reset 06h 0bh 0dh 12h flow chart
ST7625 ver 1.6 124/160 2008/07 9.1.52 frm8sel: frame freq. in temp. range (idel-8 color) (f1h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 1 1 1 1 0 0 0 1 f1h 1 st parameter 1 1 0 - - - f8a4 f8a3 f8a2 f8a1 f8a0 range a 2 nd parameter 1 1 0 - - - f8b4 f8b3 f8b2 f8b1 f8b0 range b 3 rd parameter 1 1 0 - - - f8c4 f8c3 f8c2 f8c1 f8c0 range c 4 th parameter 1 1 0 - - - f8d4 f8d3 f8d2 f8d1 f8d0 range d description select frame freq. in normal display mode.(idle;8 c olor mode) 1 st parameter : frame freq. value set in temp range 30 (-30 ) to ta 2 nd parameter : frame freq. value set in temp range ta to tb 3 rd parameter : frame freq. value set in temp range tb to tc 4 th parameter : frame freq. value set in temp range tc to 145(90 ) restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status fa[4:0] fb[4:0] fc[4:0] fd[4:0] power on sequence 06h 0bh 0dh 12h s/w reset 06h 0bh 0dh 12h h/w reset 06h 0bh 0dh 12h flow chart 1st parameter. f8a[4:0] 2nd parameter. f8b[4:0] 3rd parameter. f8c[4:0] 4th parameter. f8d[4:0] frm8sl
ST7625 ver 1.6 125/160 2008/07 9.1.53 tmprng: temp. range set for frame freq. adj. (f2h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 1 1 1 1 0 0 1 0 f2h 1 st parameter 1 1 0 - ta6 ta5 ta4 ta3 ta2 ta1 ta0 range a 2 nd parameter 1 1 0 - tb6 tb5 tb4 tb3 tb2 tb1 tb0 range b 3 rd parameter 1 1 0 - tc6 tc5 tc4 tc3 tc2 tc1 tc0 range c description temp. range set for automatic frame freq. adj. oper ation according the current temp. value. 1 st parameter: temp. range a value set 2 nd parameter: temp. range b value set 3 rd parameter: temp. range c value set ta/tb/tc temperature( ) + 40 = ta/tb/tc[6:0] example: if ta wants to be set at 24 , ta[6:0]=24+40=64(40h), restriction -40 ta ta+th tb tb+th tc 87 register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default default value status ta[6:0] tb[6:0] tc[6:0] power on sequence 1eh 28h 32h s/w reset 1eh 28h 32h h/w reset 1eh 28h 32h flow chart
ST7625 ver 1.6 126/160 2008/07 9.1.54 tmphys: temp.hysteresis set for frame freq. adj.(f3h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 hex command 0 1 0 1 1 1 1 0 0 1 1 f3h 1 st parameter 1 1 0 - - - - th3 th2 th1 th0 description temp. hysteresis range set for frame freq. adj. parameter th[3:0] is used to set temp. hysteresis ra nge. the relationship between temp. state and temp. rang e value is shown below. temp range value temp rising state temp falling state freq. changing point a ta[6:0]+th[3:0] ta[6:0] freq. changing point b tb[6:0]+th[3:0] tb[6:0] freq. changing point c tc[6:0]+th[3:0] tc[6:0] th temperature( ) - 1 = th[3:0] example: if th wants to set 5 , th[3:0]=5 -1=4. restriction temp. hysteresis value should be smaller than the g ap of temp. range. register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value(th[3:0]) power on sequence 04h s/w reset 04h h/w reset 04h flow chart
ST7625 ver 1.6 127/160 2008/07 9.1.55 tempsel: temp. set(f4h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex tempsel 0 1 0 1 1 1 1 0 1 0 0 (f4h) 1 st parameter 1 1 0 mt13 mt12 mt11 mt10 mt03 mt02 mt01 mt00 mt1x: (-24 o c to -32 o c ) mt0x: (-32 o c to -40 o c ) 2 nd parameter 1 1 0 mt33 mt32 mt31 mt30 mt23 mt22 mt21 mt20 mt3x: (-8 o c to -16 o c ) mt2x: (-16 o c to -24 o c ) 3 rd parameter 1 1 0 mt53 mt52 mt51 mt50 mt43 mt42 mt41 mt40 mt5x: (8 o c to 0 o c ) mt4x: (0 o c to -8 o c ) 4 th parameter 1 1 0 mt73 mt72 mt71 mt70 mt63 mt62 mt61 mt60 mt7x: (24 o c to16 o c ) mt6x: (16 o c to 8 o c ) 5 th parameter 1 1 0 mt93 mt92 mt91 mt90 mt83 mt82 mt81 mt80 mt9x: (40 o c to 32 o c ) mt8x: (32 o c to 24 o c ) 6 th parameter 1 1 0 mtb3 mtb2 mtb1 mtb0 mta3 mta2 mta1 mta0 mtbx: (56 o c to 48 o c ) mtax: (48 o c to 40 o c ) 7 th parameter 1 1 0 mtd3 mtd2 mtd1 mtd0 mtc3 mtc2 mtc1 mtc0 mtdx: (72 o c to 64 o c ) mtcx: (64 o c to 56 o c ) 8 th parameter 1 1 0 mtf3 mtf2 mtf1 mtf0 mte3 mte2 mte1 mte0 mtfx: (87 o c to 80 o c ) mtex: (80 o c to 72 o c ) note: - dont care description this command defines temperature gradient compensat ion coefficient. for this command detail description and opearation, please see figur e 7.8. parameter n mt n 3 mt n 2 mt n 1 mt n 0 voltage / o c 0 0 0 0 0 5 mv / o c 1 0 0 0 1 0 mv / o c 2 0 0 1 0 -5 mv / o c 3 0 0 1 1 -10 mv / o c : : : : : : : : : : : : : : : : : : 12 1 1 0 0 -55 mv / o c 13 1 1 0 1 -60 mv / o c 14 1 1 1 0 -65 mv / o c 15 1 1 1 1 -70 mv / o c voltage/ (+/ - 5mv tolerance) restriction please refer to the absolute maximum ratings for op erating temperature range register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes
ST7625 ver 1.6 128/160 2008/07 default status default value (mtn[3:0]) power on sequence s/w reset h/w reset 1 st parameter : ffh 2 nd parameter : 36h 3 rd parameter : 04h 4 th parameter : 00h 5 th parameter : 33h 6 th parameter : 42h 7 th parameter : c4h 8 th parameter : 59h flow chart
ST7625 ver 1.6 129/160 2008/07 9.1.56 thys : temperature detection threshold(f7h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex thys 0 1 0 1 1 1 1 0 1 1 1 (f7h) parameter 1 1 0 thys7 thys6 thys5 thys4 thys3 thys2 thys1 thys0 - note: - dont care description temperature detection threshold setting. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value d[7:0] power on sequence 06h s/w reset 06h h/w reset 06h flow chart
ST7625 ver 1.6 130/160 2008/07 9.1.57 frame set: frame pwm set (f9h) command a0 /rd /wr d7 d6 d5 d4 d3 d2 d1 d0 hex frame set 0 1 0 1 1 1 1 1 0 0 1 (f9h) 1 st parameter 1 1 0 - - - p14 p13 p12 p11 p10 - 2 nd parameter 1 1 0 - - - p24 p23 p22 p21 p20 - : : : : : : : : : : : : - 15 th parameter 1 1 0 - - - p154 p153 p152 p151 p150 - 16 th parameter 1 1 0 - - - p164 p163 p162 p161 p160 - note: - dont care description this command is used to set frame pwm. restriction register availability status availability normal mode on, idle mode off, sleep out yes normal mode on, idle mode on, sleep out yes partial mode on, idle mode off, sleep out yes partial mode on, idle mode on, sleep out yes sleep in yes default status default value power on sequence refer to the table on next page. s/w reset refer to the table on next page. h/w reset refer to the table on next page. flow chart
ST7625 ver 1.6 131/160 2008/07 note: the default value of rgb level set rgb set rgb level0 00 rgb level1 01 rgb level2 02 rgb level3 04 rgb level4 06 rgb level5 07 rgb level6 09 rgb level7 0a rgb level8 0b rgb level9 0c rgb level10 0d rgb level11 0f rgb level12 11 rgb level13 12 rgb level14 17 rgb level15 1a all the modulation range of each level for each fram e is from 00h to 1fh.
ST7625 ver 1.6 132/160 2008/07 10. specifications 10.1 absolute maximum ratings (v ss = 0v) item symbol value unit supply voltage (1) v dd , v dd1 - 0.3 ~ + 3.0 v supply voltage (1) v dd2 , v dd3 , v dd4 , v dd5 - 0.3 ~ + 3.6 v supply voltage (2) v lcd (v0-vss) - 0.3 ~ + 18.0 v supply voltage (3) vm ax (v0- xv0 ) - 0.3 ~ + 18.0 v input voltage range v in - 0.3 ~ v dd + 0.3 v output voltage range v o - 0.3 ~ v dd + 0.3 v operating temperature range t opr - 30 ~ + 85 c storage temperature range t stg - 40 ~ + 125 c note: 1. voltages are all based on vss = 0v. 2. voltage relationship: v0. vg. vm. vss. xv0 must always be satisfied. 3. external v0,xv0
ST7625 ver 1.6 133/160 2008/07 10.2 dc characteristics 10.2.1 basic characteristics (v ss =0v, ta = -30 to 85c) parameter symbol conditions related pins min typ max unit logic operating voltage v ddi - *2) vdd,vdd1 1.65 1.8 3.0 analog operating voltage v dda - *2) vdd2,3,4,5 2.4 2.75 3.3 driving voltage input v lcd v0 C xv0 *3) v0, xv0 - - 18.0 high level input voltage v ih *1) *2) 0.7v dd - v dd low level input voltage v il - *1) *2) v ss - 0.3v dd high level output voltage v oh i oh = -1.0ma 0.8v dd - v dd low level output voltage v ol i ol = +1.0ma *2) si v ss - 0.2v dd v input leakage current i il v in = v dd or v ss *1), *2) -1.0 - +1.0 a driver on resistance (seg) r onseg vg = 2.4v,ta= 25 c, v=10% s0 to s305 - 0.7 driver on resistance (com) r oncom v0 = 12.0v,ta= 25 c, v=10% c0 to c95 - 0.5 k frame rate fr ta=25c, n-line=0x00,duty=96, fr=0x12 - 77 - hz note: *1) applies to if1, if2, if3, /cs, /rst, /wr, /rd, a0( scl) and d15-d2, d1 (a0) ,d0(si) pins *2) *3) when the measurements are performed with lc d module, measurement points are like below.
ST7625 ver 1.6 134/160 2008/07 10.2.2 current consumption (bare die) rating test pattern symbol condition min. typ. max. units notes display pattern normal iss 500 a power down iss vddi=1.8v, vdda=2.8v, vop=11v, booster=8x, bias=1/9, booster efficiency=01, ta = 25c. 10 25 a note: the current consumption is dc characteristics.
ST7625 ver 1.6 135/160 2008/07 11. timing characteristics 11.1 parallel interface characteristics bus (8080- series mcu) figure 11.1 parallel interface characteristics bus( 8080-series mcu) (v dd =2.8v, ta= 25c, die) rating item signal symbol condition min. max. units address hold time tah8 10 address setup time a0 taw8 15 system cycle time (write) tcyc8 145 /wr l pulse width (write) tcclw 55 /wr h pulse width (write) wr tcchw 90 system cycle time (read) tcyc8 175 /rd l pulse width (read) tcclr 55 /rd h pulse width (read) rd (fm) tcchr when read from frame memory 120 write data setup time tds8 50 write data hold time tdh8 10 read access time tacc8 cl = 16 pf 45 read output disable time d0 to d7 toh8 cl = 16 pf 35 ns
ST7625 ver 1.6 136/160 2008/07 (v dd =1.8v, ta= 25c, die) rating item signal symbol condition min. max. units address hold time tah8 10 address setup time a0 taw8 20 system cycle time (write) tcyc8 245 /wr l pulse width (write) tcclw 100 /wr h pulse width (write) wr tcchw 145 system cycle time (read) tcyc8 250 /rd l pulse width (read) tcclr 70 /rd h pulse width (read) rd (fm) tcchr when read from frame memory 180 write data setup time tds8 70 write data hold time tdh8 20 read access time tacc8 cl = 16 pf 60 read output disable time d0 to d7 toh8 cl = 16 pf 40 ns *1 the input signal rise time and fall time (tr, tf ) is specified at 15 ns or less. when the system cy cle time is extremely fast, (tr +tf) (tcyc8 C tcclw C tcchw) for (tr + tf) (tcyc8 C tcclr C tcchr) are specified. *2 all timing is specified using 20% and 80% of vdd a s the reference. *3 tcclw and tcclr are specified as the overlap bet ween /cs being l and wr and rd being at the l le vel.
ST7625 ver 1.6 137/160 2008/07 11.2 parallel interface characteristics bus (6800- series mcu) figure 11.2 parallel interface characteristics (680 0-series mcu) (v dd =2.8v, ta= 25c, die) rating item signal symbol condition min. max. units address hold time tah6 10 address setup time a0 taw6 20 system cycle time (write) tcyc6 155 /wr l pulse width (write) tewhw 95 /wr h pulse width (write) e tewlw 60 system cycle time (read) tcyc6 175 /rd l pulse width (read) tewhr 110 /rd h pulse width (read) rd (fm) tewhr when read from frame memory 65 write data setup time tds6 50 write data hold time tdh6 10 read access time tacc8 cl = 16 pf 55 read output disable time d0 to d7 toh8 cl = 16 pf 50 ns
ST7625 ver 1.6 138/160 2008/07 (v dd =1.8v, ta= 25c, die) rating item signal symbol condition min. max. units address hold time tah6 15 address setup time a0 taw6 20 system cycle time (write) tcyc6 210 /wr l pulse width (write) tewhw 130 /wr h pulse width (write) e tewlw 80 system cycle time (read) tcyc6 300 /rd l pulse width (read) tewhr 200 /rd h pulse width (read) rd (fm) tewhr when read from frame memory 100 write data setup time tds6 55 write data hold time tdh6 10 read access time tacc8 cl = 16 pf 100 read output disable time d0 to d7 toh8 cl = 16 pf 80 ns *1 the input signal rise time and fall time (tr, tf ) is specified at 15 ns or less. when the system cy cle time is extremely fast, (tr +tf) (tcyc6 C tewlw C tewhw) for (tr + tf) (tcyc6 C tewlr C tewhr) are specified. *2 all timing is specified using 20% and 80% of vdd a s the reference. *3 tewlw and tewlr are specified as the overlap bet ween /cs being l and e.
ST7625 ver 1.6 139/160 2008/07 11.3 serial interface characteristics (3-pin seria l) figure 11.3 3-pin serial interface characteristics (v dd =2.8v, ta= 25c, die) rating item signal symbol condition min. max. units serial clock period (write) tscycw 80 scl h pulse width (write) tshw 25 scl l pulse width (write) scl tslw 25 data setup time tsds 20 data hold time si tsdh 20 read access time tacc cl = 16 pf 70 read output disable time toh cl = 16 pf 70 cs-scl time tcss 25 cs-scl time /cs tcsh 25 ns
ST7625 ver 1.6 140/160 2008/07 (v dd =1.8v, ta= 25c, die) rating item signal symbol condition min. max. units serial clock period (write) tscycw 100 scl h pulse width (write) tshw 35 scl l pulse width (write) scl tslw 35 data setup time tsds 30 data hold time si tsdh 30 read access time tacc cl = 16 pf 90 read output disable time toh cl = 16 pf 70 cs-scl time tcss 35 cs-scl time /cs tcsh 35 ns *1 the input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 all timing is specified using 20% and 80% of vdd a s the standard.
ST7625 ver 1.6 141/160 2008/07 11.4 serial interface characteristics (4-pin seria l) /cs scl si (din) si (dout) v ih v ih v ih v ih v il v il v il v il t css t scycw /t scycr t csh t chw t scc t slw /t slr t shw /t shr t sds t sdh t acc t oh t sas t sah a0 figure 11.4 4-pin serial interface characteristics (v dd =2.8v, ta= 25c, die) rating item signal symbol condition min. max. units serial clock period (write) tscycw 80 scl h pulse width (write) tshw 25 scl l pulse width (write) scl tslw 25 address setup time tsas 15 address hold time a0 tsah 20 data setup time tsds 20 data hold time tsdh 20 read access time tacc cl = 16 pf 70 read output disable time si toh cl = 16 pf 50 cs-scl time tcss 25 cs-scl time /cs tcsh 25 ns
ST7625 ver 1.6 142/160 2008/07 (v dd =1.8v, ta=25c, die) rating item signal symbol condition min. max. units serial clock period (write) tscycw 100 scl h pulse width (write) tshw 35 scl l pulse width (write) scl tslw 35 address setup time tsas 25 address hold time a0 tsah 30 data setup time tsds 30 data hold time si tsdh 30 read access time tacc cl = 16 pf 90 read output disable time toh cl = 16 pf 70 cs-scl time tcss 35 cs-scl time /cs tcsh 35 ns *1 the input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 all timing is specified using 20% and 80% of vdd a s the standard.
ST7625 ver 1.6 143/160 2008/07 11.5 ouput access/disable timing measurement metho d parallel interface (8080-series) serial interface (3-line) note: 1. pull-up/pull-down resistor: 3k 5% ; pull-up/pull-down capacitor: 16pf 10% 2. capacitances and resistances of the oscilloscope s probe must be included externals components in t hese measurements.
ST7625 ver 1.6 144/160 2008/07 12. reset timing (v ss =0v, v ddi =1.65v to 3.0v, v dda =2.4v to 3.3v,ta =25c ) rating item signal symbol condition min. max. units reset l pulse width /rst trw 10 us reset time trt 5 (*note 5) ms 120 (*note 6,7) ms notes: 1. the reset cancel includes also required time for loading id bytes, vcom setting and other settings f rom eeprom (or similar device) to registers. this loading is done every time when there is hw reset cancel time (trt) within 5 ms after a rising edge of /rst 2. spike due to an electrostatic discharge on /rst li ne does not cause irregular system reset according to the table below: /rst pulse action shorter than 5 s reset rejected longer than 9 s reset between 5 s and 9 s reset starts 3. during the resetting period, the display will be blanked (the display is entering blanking sequence , which maximum time is 120 ms, when reset starts in sleep out Cmode. the display remains the blank state in sleep in -m ode.) and then return to default condition for hardware reset. 4. spike rejection also applies during a valid reset pulse as shown below:
ST7625 ver 1.6 145/160 2008/07 5. when reset applied during sleep in mode. 6. when reset applied during sleep out mode. 7. it is necessary to wait 120msec after releasing rst before sending commands. also sleep out command c annot be sent for 120msec.
ST7625 ver 1.6 146/160 2008/07 13. the mpu interface (reference examples) the ST7625 series can be connected to either 8080 seri es mpus or to 6800 series mpus. moreover, using the s erial interface it is possible to operate the ST7625 serie s chips with fewer signal lines. the display area can be enlarged by using multiple ST7625 series chips. when this is done, the chip sele ct signal can be used to select the individual ics to access. (1) 8080 series mpus mpu ST7625 (2) 6800 series mpus a0 d0tod 15 rd wr res v cc gnd mpu a0 d 0 tod15 e (/ rd) r /w (/ wr) / res v dd v ss ST7625 reset v dd v ss if 1 if 2 if 3 /cs /cs
ST7625 ver 1.6 147/160 2008/07 (3) using the serial interface (4-line interface) mpu ST7625 (4) using the serial interface (3-line interface) mpu ST7625
ST7625 ver 1.6 148/160 2008/07 a- application note a1 C 8080-16bit / com interlace mode vpp 31 vpp 32 vdd 33 cl 34 cls 35 vss 36 vdd 37 a0 38 rw_wr 39 d0 40 d1 41 d2 42 d3 43 d4 44 d5 45 d6 46 d7 47 d8 48 d9 49 d10 50 d11 51 d12 52 d13 53 d14 54 d15 55 vss 56 vdd 57 e_rd 58 rst 59 csel 60 i f1 61 i f2 62 i f3 63 vss 64 vdd 65 /cs 66 tcap 67 vdd 68 vdd 71 vdd1 72 vdd1 73 vss1 74 vss1 75 vss 76 vss 79 vss2 80 vss2 91 vss4 92 vss4 93 vdd3 94 vdd3 95 vdd4 96 vdd4 97 vdd5 98 vdd5 105 vdd2 106 vdd2 115 v4 116 vref 117 v0in 118 v0in 121 v0s 122 v0out 123 v0out 124 xv0out 125 xv0out 126 xv0s 127 xv0in 128 xv0in 131 v3out 132 v3out 133 v3s 134 v3in 135 v3in 142 com95/com1 143 com91/com9 147 com0/com 0 30 com4/com 8 26 ST7625 ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ seg305 191 seg304 192 seg0 496 seg1 495 c1 1uf/25v c2 1uf/15v note : 8080-16 bit interface if1: if2: if3 = 1 : 1: 1 cls='1',using internal colock vddi operation voltage range 1.65v to 3.0v vdd operation voltage range 2.4 v to 3.3 v vop=9~12v ito fpc fpc_interface vpp a0 /wr d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 /rd rst /cs vd di vss vd d v0 test point test point com1 com0 xv0 test point c3 1uf/15v 8080-16 bit if1:if2:if3=1:1:1
ST7625 ver 1.6 149/160 2008/07 a2 C6800-16bit / com interlace mode vpp 31 vpp 32 vdd 33 cl 34 cls 35 vss 36 vdd 37 a0 38 rw_wr 39 d0 40 d1 41 d2 42 d3 43 d4 44 d5 45 d6 46 d7 47 d8 48 d9 49 d10 50 d11 51 d12 52 d13 53 d14 54 d15 55 vss 56 vdd 57 e_rd 58 rst 59 csel 60 if1 61 if2 62 if3 63 vss 64 vdd 65 /cs 66 tcap 67 vdd 68 vdd 71 vdd1 72 vdd1 73 vss1 74 vss1 75 vss 76 vss 79 vss2 80 vss2 91 vss4 92 vss4 93 vdd3 94 vdd3 95 vdd4 96 vdd4 97 vdd5 98 vdd5 105 vdd2 106 vdd2 115 v4 116 vref 117 v0in 118 v0in 121 v0s 122 v0out 123 v0out 124 xv0out 125 xv0out 126 xv0s 127 xv0in 128 xv0in 131 v3out 132 v3out 133 v3s 134 v3in 135 v3in 142 com95/com1 143 com91/com9 147 com0/com0 30 com4/com8 26 ST7625 ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ seg305 191 seg304 192 seg0 496 seg1 495 c1 1uf/25v c2 1uf/15v note : 6800-16 bit interface if1: if2: if3 = 1 : 0 : 0 cls='1',using internal colock vddi operation voltage range 1.65v to 3.0v vdd operation voltage range 2.4 v to 3.3 v vop=9~12v ito fpc fpc_interface vpp a0 rw d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 e rst /cs vd di vss vd d v0 test point test point com1 com0 xv0 test point c3 1uf/15v 6800-16 bit if1:if2:if3=1:0:0
ST7625 ver 1.6 150/160 2008/07 a3 C8080-8bit / com interlace mode vpp 31 vpp 32 vdd 33 cl 34 cls 35 vss 36 vdd 37 a0 38 rw_wr 39 d0 40 d1 41 d2 42 d3 43 d4 44 d5 45 d6 46 d7 47 d8 48 d9 49 d10 50 d11 51 d12 52 d13 53 d14 54 d15 55 vss 56 vdd 57 e_rd 58 rst 59 csel 60 i f1 61 i f2 62 i f3 63 vss 64 vdd 65 /cs 66 tcap 67 vdd 68 vdd 71 vdd1 72 vdd1 73 vss1 74 vss1 75 vss 76 vss 79 vss2 80 vss2 91 vss4 92 vss4 93 vdd3 94 vdd3 95 vdd4 96 vdd4 97 vdd5 98 vdd5 105 vdd2 106 vdd2 115 v4 116 vref 117 v0in 118 v0in 121 v0s 122 v0out 123 v0out 124 xv0out 125 xv0out 126 xv0s 127 xv0in 128 xv0in 131 v3out 132 v3out 133 v3s 134 v3in 135 v3in 142 com95/com1 143 com91/com9 147 com0/com 0 30 com4/com 8 26 ST7625 ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ seg305 191 seg304 192 seg0 496 seg1 495 c1 1uf/25v c2 1uf/15v note : 8080-8 bit interface if1: if2: if3 = 1 : 1: 0 cls='1',using internal colock vddi operation voltage range 1.65v to 3.0v vdd operation voltage range 2.4 v to 3.3 v vop=9~12v ito fpc fpc_interface vpp a0 / wr d0 d1 d2 d3 d4 d5 d6 d7 / rd rst / cs vd di vss vd d v0 test point test point com1 com0 xv0 test point c3 1uf/15v 8080-8 bit if1:if2:if3=1:1:0
ST7625 ver 1.6 151/160 2008/07 a4 C 6800-8bit / com interlace mode vpp 31 vpp 32 vdd 33 cl 34 cls 35 vss 36 vdd 37 a0 38 rw_wr 39 d0 40 d1 41 d2 42 d3 43 d4 44 d5 45 d6 46 d7 47 d8 48 d9 49 d10 50 d11 51 d12 52 d13 53 d14 54 d15 55 vss 56 vdd 57 e_rd 58 rst 59 csel 60 if1 61 if2 62 if3 63 vss 64 vdd 65 /cs 66 tcap 67 vdd 68 vdd 71 vdd1 72 vdd1 73 vss1 74 vss1 75 vss 76 vss 79 vss2 80 vss2 91 vss4 92 vss4 93 vdd3 94 vdd3 95 vdd4 96 vdd4 97 vdd5 98 vdd5 105 vdd2 106 vdd2 115 v4 116 vref 117 v0in 118 v0in 121 v0s 122 v0out 123 v0out 124 xv0out 125 xv0out 126 xv0s 127 xv0in 128 xv0in 131 v3out 132 v3out 133 v3s 134 v3in 135 v3in 142 com95/com1 143 com91/com9 147 com0/com 0 30 com4/com 8 26 ST7625 ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ seg305 191 seg304 192 seg0 496 seg1 495 c1 1uf/25v c2 1uf/15v note : 6800-8 bit interface if1: if2: if3 = 0 : 1 : 1 cls='1',using internal colock vddi operation voltage range 1.65v to 3.0v vdd operation voltage range 2.4 v to 3.3 v vop=9~12v ito fpc fpc_interface vpp a0 rw d0 d1 d2 d3 d4 d5 d6 d7 e rst /cs vd di vss vd d v0 test point test point com1 com0 xv0 test point c3 1uf/15v 6800-8 bit if1:if2:if3=0:1:1
ST7625 ver 1.6 152/160 2008/07 a5 C 4l spi / com interlace mode vpp 31 vpp 32 vdd 33 cl 34 cls 35 vss 36 vdd 37 a0 38 rw_wr 39 d0 40 d1 41 d2 42 d3 43 d4 44 d5 45 d6 46 d7 47 d8 48 d9 49 d10 50 d11 51 d12 52 d13 53 d14 54 d15 55 vss 56 vdd 57 e_rd 58 rst 59 csel 60 i f1 61 i f2 62 i f3 63 vss 64 vdd 65 /cs 66 tcap 67 vdd 68 vdd 71 vdd1 72 vdd1 73 vss1 74 vss1 75 vss 76 vss 79 vss2 80 vss2 91 vss4 92 vss4 93 vdd3 94 vdd3 95 vdd4 96 vdd4 97 vdd5 98 vdd5 105 vdd2 106 vdd2 115 v4 116 vref 117 v0in 118 v0in 121 v0s 122 v0out 123 v0out 124 xv0out 125 xv0out 126 xv0s 127 xv0in 128 xv0in 131 v3out 132 v3out 133 v3s 134 v3in 135 v3in 142 com95/com1 143 com91/com9 147 com0/com0 30 com4/com8 26 ST7625 ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ seg305 191 seg304 192 seg0 496 seg1 495 c1 1uf/25v c2 1uf/15v note : 8 bit spi (4 line) if1: if2: if3 = 0 : 0: 0 cls='1',using internal colock vddi operation voltage range 1.65v to 3.0v vdd operation voltage range 2.4 v to 3.3v vop=9~12v ito fpc fpc_interface vpp / rd rst / cs vd di vss vd d v0 test point test point com1 com0 xv0 test point si scl c3 1uf/15v a0 8 bit 4spi if1:if2:if3=0:0:1
ST7625 ver 1.6 153/160 2008/07 a6 C 3l spi / com interlace mode vpp 31 vpp 32 vdd 33 cl 34 cls 35 vss 36 vdd 37 a0 38 rw_wr 39 d0 40 d1 41 d2 42 d3 43 d4 44 d5 45 d6 46 d7 47 d8 48 d9 49 d10 50 d11 51 d12 52 d13 53 d14 54 d15 55 vss 56 vdd 57 e_rd 58 rst 59 csel 60 i f1 61 i f2 62 i f3 63 vss 64 vdd 65 /cs 66 tcap 67 vdd 68 vdd 71 vdd1 72 vdd1 73 vss1 74 vss1 75 vss 76 vss 79 vss2 80 vss2 91 vss4 92 vss4 93 vdd3 94 vdd3 95 vdd4 96 vdd4 97 vdd5 98 vdd5 105 vdd2 106 vdd2 115 v4 116 vref 117 v0in 118 v0in 121 v0s 122 v0out 123 v0out 124 xv0out 125 xv0out 126 xv0s 127 xv0in 128 xv0in 131 v3out 132 v3out 133 v3s 134 v3in 135 v3in 142 com95/com1 143 com91/com9 147 com0/com 0 30 com4/com 8 26 ST7625 ~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ seg305 191 seg304 192 seg0 496 seg1 495 c1 1uf/25v c2 1uf/15v note : 9 bit spi (3 line) if1: if2: if3 = 0 : 0: 1 cls='1',using internal colock vddi operation voltage range 1.65v to 3.0v vdd operation voltage range 2.4 v to 3.3 v vop=9~12v ito fpc fpc_interface vpp rst /cs vd di vss vd d v0 test point test point com1 com0 xv0 test point si scl c3 1uf/15v 9 bit 3spi if1:if2:if3=0:0:1
ST7625 ver 1.6 154/160 2008/07 com0/com 0 30 com4/com 8 26 ST7625 seg305 191 seg304 192 seg0 496 seg1 495 com1/com 2 29 com2/com 4 28 com3/com 6 27 com5/com10 25 com6/com12 24 com29/com58 1 com28/com56 2 com95/com1 143 com91/com9 147 com94/com3 144 com93/com5 145 com92/com7 146 com5/com10 148 com6/com12 149 com66/com59 172 com67/com57 171 com30/com60 514 com31/com62 513 com32/com64 512 com47/com94 497 com45/com90 499 com46/com92 498 ~ ~ ~ ~ com48/com95 190 com49/com93 189 com50/com91 188 com65/com61 173 com63/com65 175 com64/com63 174 ~ ~ ~ ~ ST7625_com 0 1 2 3 4 5 90 91 92 93 94 95 csel="1" panel
ST7625 ver 1.6 155/160 2008/07 a7 - power on flow and sequence poweron keepingthe/rstpin="l"and waitingforstabilizingthepower /rstpin="h"andwaitforresetcomplete (>120ms) internal state t rw /rst poweron vddi (digital) reset > 10us normalsate vdda (analog) trtw trtw>=0 internal state t rw /res poweron vdd i (digital) reset > 10us normalsate vdd a (analog) trtw trtw>=0 t rw t rw
ST7625 ver 1.6 156/160 2008/07 a8 - power off flow and sequence sleepin poweroff(t r >120ms) normal state endofpoweroff keeping/rstpin= l internal state t r /rst normal state vdda (analog) reset t r > 120ms poweroff keepthe/rst=low vddi (digital) tfpw tfpw>=0
ST7625 ver 1.6 157/160 2008/07 a9 Cotp burning flow: hwreset restartST7625module removepowerfrom vpp delay120ms checkdisplay performance initialST7625 showimageand finetunevop otpwriting + c1 c2 key adjustvopoffset (softwarecodingflow) vppconnectto 7.5v~7.75v
ST7625 ver 1.6 158/160 2008/07 a10 C software coding flow void initial_lcd_module ( void ) { //-----------disable autoread + manual read once -- --------------------------- write(command,0xd7); // auto load set write(data,0x1f); // auto load disable write(command,0xe0); // ee read/write mode write(data,0x00); // set read mode delayms(10); // delay 10ms write(command,0xe3); // read active delayms(20); // delay 20ms write(command,0xe1); // cancel control //---------------------------------- sleep out ---- ------------------------------------- write(command, 0x28 ); // display off write(command, 0x11 ); // sleep out delayms(50); // delay 50ms //----------------------------vop setting---------- -------------------------------------- write(command,0xc0); //set vop by initial module write(data, 0xb9); //vop = 11v write(data, 0x00); // base on module //----------------------------set register-------- --------------------------- ------- write(command,0xc3); // bias select write(data,0x02); // 1/10 bias, base on module write(command,0xc4); // setting booster times write(data,0x07); // booster x 8 write(command,0xc5); // booster eff write(data,0x01); // be = 0x01 (level 2) write(command,0xcb); // vg with booster x2 control write(data,0x01); // vg from vdd2 write(command,0xd0); // analog circuit setting write(data,0x1d); // write(command,0x3a); // color mode = 65k write(data,0x05); // write(command,0x36); // memory access control // write(data,0x08); write(command, 0xb5 ); // n-line write(data, 0x01); // rst, 2-line inversion write(command,0xf7 ); // command for temp sensitivity. write(data,0x06); // 1. set gamma table for module, please refer spec se tting. 2. set temp compensation for module, please refer s pec setting. write(command,0x2a); // set col by module write(data,0x00); // 0~95 write(data,0x5f); // write(command,0x2b); // set page by module write(data,0x00); // 0~95 write(data,0x5f); // write(command, 0x29 ); // display on }
ST7625 ver 1.6 159/160 2008/07 void otp_writing ( void ) { //--------------------------------display off------ ---------------------------------- write(command, 0x28 ); // display off delayms(50); // delay 50ms //--------------------------------otp writing------ ---------------------------------- write( command, 0x00f0 ); // keep frame rate write( data, 0x0012 ); // write( data, 0x0012 ); write( data, 0x0012 ); write( data, 0x0012 ); write( command, 0x00e4 ); //otp selection write( data, 0x0058 ); // select otp write( command, 0x00e5 ); // set otp writing setup write( data, 0x0009 ); write( command, 0x00e0 ); // read/write mode setting write( data, 0x0020 ); // set write mode delayms(100); //delay 100ms write( command, 0x00e2 ); // write active delayms(100); //delay 100ms write( command, 0x00e1 ); } note: #1. in this section+ & - key button, please exe cute write(command,0xc1) to increase one step at vo p and execute write(command,0xc2) to decrease one step at vop, if necessary. #2. tc is turned on in burning flow. if lcd module is too dark or bright, its an effect of backlight . #3. the otp function can not be guaranteed after bu rned over 4 times. //--------------------------------fine tune vop off set---------------------------------------- void fine_tune_vop ( void ) { show_image(); //display a image //------------------------------------ display on - ---------------------------------------------- write(command, 0x29 ); // display on //--------------------------------fine tune vop off set---------------------------------------- write( command, 0xc1); or write( command, 0xc2); //fine tuning vop here by command 0xc1(vopoffsetinc),0xc2(vopoffsetdec). note#1 }
ST7625 ver 1.6 160/160 2008/07 ST7625 specification revision history version date description 0.x preliminary version 1.0 2007/2/14 first issue 1.1 2007/5/9 redefine the programming mechanism of non-volatilit y memory. 1.2 2007/6/5 1. add cmd e5 description 2. 8080 interface timing modify 1.3 2007/8/22 add ST7625-g3 and ST7625-g4 description. 1.4 2008/01 1. update current consumption table 2. update logic operating voltage range 3 modify the voltage range in application note. 4. remove 256 color 16bits mode 1.5 2008/03 1. modify description in software codin g flow. 1.6 2008/07 1. modify ac/dc characteristics condition 2. remove cl pin function 3. add read access time and output disable time tim ing data

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